Paper Abstract and Keywords |
Presentation |
2008-11-17 15:50
Multi-Rate Compatible High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit Akiyuki Nagashima, Yuta Imai, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-66 DC2008-34 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Low Density Parity Check (LDPC) code is expected to be an error correcting code for next generation networks since it shows high error correcting performance and is incorporated in IEEE802.11n the next standard of wireless network. In this paper, we propose a multi-rate compatible irregular LDPC decoder enhancing column operation parallelism.
Focusing on column-wise parallelism of column operations, uplift usage
rate of operational unit and throughput by calculating all inputs
simultaneously. The decoder achieves 12% savings in area and 81 % increase in throughput compared to recent architectures. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
LDPC decoder / Irregular / Multi-Rate / column operation / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 298, VLD2008-66, pp. 37-42, Nov. 2008. |
Paper # |
VLD2008-66 |
Date of Issue |
2008-11-10 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2008-66 DC2008-34 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2008-11-17 - 2008-11-19 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kitakyushu Science and Research Park |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2008 ―New field of VLSI design― |
Paper Information |
Registration To |
VLD |
Conference Code |
2008-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Multi-Rate Compatible High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit |
Sub Title (in English) |
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Keyword(1) |
LDPC decoder |
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Irregular |
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Multi-Rate |
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column operation |
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1st Author's Name |
Akiyuki Nagashima |
1st Author's Affiliation |
Waseda University (Waseda Univ.) |
2nd Author's Name |
Yuta Imai |
2nd Author's Affiliation |
Waseda University (Waseda Univ.) |
3rd Author's Name |
Nozomu Togawa |
3rd Author's Affiliation |
Waseda University (Waseda Univ.) |
4th Author's Name |
Masao Yanagisawa |
4th Author's Affiliation |
Waseda University (Waseda Univ.) |
5th Author's Name |
Tatsuo Ohtsuki |
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Waseda University (Waseda Univ.) |
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Speaker |
Author-1 |
Date Time |
2008-11-17 15:50:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2008-66, DC2008-34 |
Volume (vol) |
vol.108 |
Number (no) |
no.298(VLD), no.299(DC) |
Page |
pp.37-42 |
#Pages |
6 |
Date of Issue |
2008-11-10 (VLD, DC) |
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