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Paper Abstract and Keywords
Presentation 2008-11-17 15:50
Hardware Implementation Costs of Adaptive Routing in the Hierarchical Interconnection Network
Masahiro Kaneko, Yasuyuki Miura, Shigeyoshi Watanabe (Shonan Institute of Technology) RECONF2008-44
Abstract (in Japanese) (See Japanese page) 
(in English) By progress of VLSI technology, "On-Chip-Multiprocessor" which processes in parallel on a wafer has been realized, and a hierarchical interconnection network TESH was proposed. Three types of adaptive routing algorithms of TESH were proposed and their availability was verified by software simulation. However, it has not verified about the increase of the hardware cost and delay. In this paper, the two types of adaptive routing algorithms of TESH (the CS algorithm and the LS algorithm) are designed by VHDL and the delay and hardware cost are evaluated.
Keyword (in Japanese) (See Japanese page) 
(in English) Interconnection Network / TESH / Routing Algorithm / / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 300, RECONF2008-44, pp. 33-38, Nov. 2008.
Paper # RECONF2008-44 
Date of Issue 2008-11-10 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2008-44

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2008-11-17 - 2008-11-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu Science and Research Park 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2008 ―New field of VLSI design― 
Paper Information
Registration To RECONF 
Conference Code 2008-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Hardware Implementation Costs of Adaptive Routing in the Hierarchical Interconnection Network 
Sub Title (in English)  
Keyword(1) Interconnection Network  
Keyword(2) TESH  
Keyword(3) Routing Algorithm  
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Keyword(5)  
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1st Author's Name Masahiro Kaneko  
1st Author's Affiliation Shonan Institute of Technology (Shonan Institute of Technology)
2nd Author's Name Yasuyuki Miura  
2nd Author's Affiliation Shonan Institute of Technology (Shonan Institute of Technology)
3rd Author's Name Shigeyoshi Watanabe  
3rd Author's Affiliation Shonan Institute of Technology (Shonan Institute of Technology)
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Speaker Author-1 
Date Time 2008-11-17 15:50:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2008-44 
Volume (vol) vol.108 
Number (no) no.300 
Page pp.33-38 
#Pages 6 
Date of Issue 2008-11-10 (RECONF) 

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