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| Presentation | 2009-01-14 11:45 Local Memory Management Scheme by a Compiler for Multicore Processor Taku Momozono, Hirofumi Nakano, Masayoshi Mase, Keiji Kimura, Hironori Kasahara (Waseda Univ.) Link to ES Tech. Rep. Archives:  ICD2008-141 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper proposes a local memory management scheme for an automatic parallelizing compiler to realize effective use of a limited size of local memory. After the loop aligned decomposition and task scheduling considering data locality and parallelism, the compiler allocates data to the local memory effectively using the task scheduling result. This paper evaluates the proposed scheme on RP2 multicore for consumer electronics which has 8 SH4A processor cores. Each core integrates 32KB of local data memory and 64KB of distributed shared memory. As the results, the proposed scheme using 8 processors gives us about 6.20 times speedup for MPEG2 encoding program, 7.25 times speedup for AAC encoding program and 7.64 times speedup for susan against the sequential execution. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Multicore / Local Memory / Automatic Parallelizing Compiler / Local Memory Management / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, pp. 69-74, Jan. 2009. | |
| Paper # | ||
| Date of Issue | 2009-01-06 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2008-141 |
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| Conference Information | |
| Committee | ICD IPSJ-ARC IPSJ-EMB |
| Conference Date | 2009-01-13 - 2009-01-14 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Shoushin Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Embedded System Platform |
| Paper Information | |
| Registration To | IPSJ-ARC |
| Conference Code | 2009-01-ICD-ARC-EMB |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Local Memory Management Scheme by a Compiler for Multicore Processor |
| Sub Title (in English) | |
| Keyword(1) | Multicore |
| Keyword(2) | Local Memory |
| Keyword(3) | Automatic Parallelizing Compiler |
| Keyword(4) | Local Memory Management |
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| 1st Author's Name | Taku Momozono |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Hirofumi Nakano |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Masayoshi Mase |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
| 4th Author's Name | Keiji Kimura |
| 4th Author's Affiliation | Waseda University (Waseda Univ.) |
| 5th Author's Name | Hironori Kasahara |
| 5th Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2009-01-14 11:45:00 |
| Presentation Time | 30 minutes |
| Registration for | IPSJ-ARC |
| Paper # | ICD2008-141 |
| Volume (vol) | vol.108 |
| Number (no) | no.375 |
| Page | pp.69-74 |
| #Pages | 6 |
| Date of Issue | 2009-01-06 (ICD) |
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