| Paper Abstract and Keywords |
| Presentation |
2009-01-29 14:10
An Efficient Cut Enumeration for Depth-Optimum Technology Mapping for LUT-based FPGAs
Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
This paper presents a top-down cut enumeration for depth-minimum technology mapping for LUT-based FPGAs. Enumerating all cuts with large size consumes long run-time because the number of cuts increases with the size of cuts. The proposed algorithm enumerates partial cuts with a guarantee that a depth-minimum network can be constructed, and runs faster than enumerating all cuts. The experimental results show that the proposed algorithm runs about $6$ times and $16$ times faster than bottom-up exhaustive enumeration for $K=8, 9$, respectively. The proposed algorithm also runs about $2$ times faster than top-down exhaustive enumeration for $K=8, 9$, respectively. Area of network derived by the set of cuts enumerated by the proposed algorithm is only $4$ \% larger than that derived by exhaustive enumeration on average, and the depth is the same. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Reconfigurable system / FPGA / technology mapping / cut enueration / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 108, pp. 57-62, Jan. 2009. |
| Paper # |
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| Date of Issue |
2009-01-22 (VLD, CPSY, RECONF) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
| Download PDF |
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| Conference Information |
| Committee |
VLD CPSY RECONF IPSJ-SLDM |
| Conference Date |
2009-01-29 - 2009-01-30 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
|
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
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| Paper Information |
| Registration To |
IPSJ-SLDM |
| Conference Code |
2009-01-VLD-CPSY-RECONF-SLDM |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
An Efficient Cut Enumeration for Depth-Optimum Technology Mapping for LUT-based FPGAs |
| Sub Title (in English) |
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| Keyword(1) |
Reconfigurable system |
| Keyword(2) |
FPGA |
| Keyword(3) |
technology mapping |
| Keyword(4) |
cut enueration |
| Keyword(5) |
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| Keyword(6) |
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| 1st Author's Name |
Taiga Takata |
| 1st Author's Affiliation |
Kyushu University (Kyushu Univ.) |
| 2nd Author's Name |
Yusuke Matsunaga |
| 2nd Author's Affiliation |
Kyushu University (Kyushu Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2009-01-29 14:10:00 |
| Presentation Time |
25 minutes |
| Registration for |
IPSJ-SLDM |
| Paper # |
VLD2008-101, CPSY2008-63, RECONF2008-65 |
| Volume (vol) |
vol.108 |
| Number (no) |
no.412(VLD), no.413(CPSY), no.414(RECONF) |
| Page |
pp.57-62 |
| #Pages |
6 |
| Date of Issue |
2009-01-22 (VLD, CPSY, RECONF) |