| Paper Abstract and Keywords |
| Presentation |
2009-02-03 09:45
A Study on Advanced FEC for LDPC Codes with Soft-Decision Decoding Takashi Mizuochi, Yoshikuni Miyata, Toshiyuki Ichikawa, Yoshiaki Konishi, Tatsuya Kobayashi, Tokoka Inoue, Kiyoshi Onohara, Soichiro Kametani, Kazuo Kubo, Hideo Yoshida, Katsuhiro Shimizu, Hiroshi Ichibangase (Mitsubishi Electric Co.) OCS2008-118 |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
Novel and strong forward error correction (FEC) for 100Gb/s optical transport networks is presented. Comparing with existing decoding method of Low-Density Parity-Check (LDPC) codes, the proposed decoding method based on cyclic-approximated delta-minimum algorithm has a potential to drastically reduce the circuit complexity. An unwanted error floor phenomenon, which usually appears in the LDPC codes having small girth, can be eliminated by concatenating with Reed-Solomon codes. A 2-bit 32 Gsample/s soft decision LSI made by SiGe BiCMOS is introduced, which is the fastest LSI reported to date. A hardware emulation technique is introduced using large scale and high speed FPGAs. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Forward error correction / 100Gb/s / LDPC codes / Soft decision decoding / Error floor / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 108, no. 423, OCS2008-118, pp. 67-72, Feb. 2009. |
| Paper # |
OCS2008-118 |
| Date of Issue |
2009-01-26 (OCS) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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| Download PDF |
OCS2008-118 |