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Paper Abstract and Keywords
Presentation 2009-02-16 13:50
A method for generating defect oriented test patterns for combinational circuits
Hiroshi Takahashi, Yoshinobu Higami, Taisuke Izumi, Takashi Aikyo, Yuzo Takamatsu (Ehime Univ.) DC2008-73
Abstract (in Japanese) (See Japanese page) 
(in English) With shrinking of LSIs, the diversification of defective mode due to defects becomes a critical issue.
Therefore, the test patterns that can detect bridging faults and open faults are needed to maintain the reliability of LSIs.
In this paper, we propose a method for generating the defect diagnostic test patterns by considering fault excitation conditions for various fault models.
The proposed method uses the defect detection probability derived from the fault excitation
functions to select the defect diagnostic test patterns form a given test pattern set.
From the experimental results, we show that the set of defect diagnostic test patterns can detect more fault models under the less number of test patterns.
Keyword (in Japanese) (See Japanese page) 
(in English) defect / defect oriented test pattern / fault excitation function / method for selecting test patterns / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 431, DC2008-73, pp. 31-36, Feb. 2009.
Paper # DC2008-73 
Date of Issue 2009-02-09 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2009-02-16 - 2009-02-16 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2009-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A method for generating defect oriented test patterns for combinational circuits 
Sub Title (in English)  
Keyword(1) defect  
Keyword(2) defect oriented test pattern  
Keyword(3) fault excitation function  
Keyword(4) method for selecting test patterns  
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Keyword(6)  
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1st Author's Name Hiroshi Takahashi  
1st Author's Affiliation Ehime University (Ehime Univ.)
2nd Author's Name Yoshinobu Higami  
2nd Author's Affiliation Ehime University (Ehime Univ.)
3rd Author's Name Taisuke Izumi  
3rd Author's Affiliation Ehime University (Ehime Univ.)
4th Author's Name Takashi Aikyo  
4th Author's Affiliation Ehime University (Ehime Univ.)
5th Author's Name Yuzo Takamatsu  
5th Author's Affiliation Ehime University (Ehime Univ.)
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Speaker Author-1 
Date Time 2009-02-16 13:50:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2008-73 
Volume (vol) vol.108 
Number (no) no.431 
Page pp.31-36 
#Pages
Date of Issue 2009-02-09 (DC) 


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