Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2009-02-16 10:25
A test pattern generation method to reduce the number of detected untestable faults on scan testing
Masayoshi Yoshimura (Kyusyu Univ.), Hiroshi Ogawa (Nihon Univ.), Yusyo Omori (Fujitsu Microelectronics), Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meizi Univ.) DC2008-69
Abstract (in Japanese) (See Japanese page) 
(in English) Scan testing is one of the most popular test method fo VLSIs. In this test, only information of the circuit structure is used, the circuit might be transferred to invalid state by the shift operations and be tested. Therefore, it is considered that scan testing is over testing. Over testing causes yield loss and the increase in number of test patterns. K cycle capture testing was proposed to decrease over testing. However, the test application time is long. In this paper, we propose a test pattern selection method for test application based on k cycle capture stuck-at test generation to reduce test application time. Our method also aim to reduce the number of detected untestable faults.
Keyword (in Japanese) (See Japanese page) 
(in English) Over testing / Sequential circuit test generation / k-cycle capture test / Test pattern selection for test application / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 431, DC2008-69, pp. 7-12, Feb. 2009.
Paper # DC2008-69 
Date of Issue 2009-02-09 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF DC2008-69

Conference Information
Committee DC  
Conference Date 2009-02-16 - 2009-02-16 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2009-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A test pattern generation method to reduce the number of detected untestable faults on scan testing 
Sub Title (in English)  
Keyword(1) Over testing  
Keyword(2) Sequential circuit test generation  
Keyword(3) k-cycle capture test  
Keyword(4) Test pattern selection for test application  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Masayoshi Yoshimura  
1st Author's Affiliation Kyusyu University (Kyusyu Univ.)
2nd Author's Name Hiroshi Ogawa  
2nd Author's Affiliation Nihon University (Nihon Univ.)
3rd Author's Name Yusyo Omori  
3rd Author's Affiliation Fujitsu Microelectronics (Fujitsu Microelectronics)
4th Author's Name Toshinori Hosokawa  
4th Author's Affiliation Nihon University (Nihon Univ.)
5th Author's Name Koji Yamazaki  
5th Author's Affiliation Meizi University (Meizi Univ.)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-2 
Date Time 2009-02-16 10:25:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2008-69 
Volume (vol) vol.108 
Number (no) no.431 
Page pp.7-12 
#Pages 6 
Date of Issue 2009-02-09 (DC) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan