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| Presentation | 2009-02-16 16:10 A Secure Scan Design Approach using Extended de Bruijn Graph Hideo Fujiwara, Marie Engelene J. Obien (NAIST)  DC2008-78 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Scan design makes digital circuits easily testable, however, it can also be exploited to be used for hacking the chip. This paper introduces a new secure scan design approach using extended de Bruijn graph, which aims to satisfy both testability and security of digital circuits. The approach is only to replace the original scan chains to modified scan registers called extended scan registers. This method requires very little area overhead and no performance overhead. Moreover, no additional keys and controller circuits outside of the scan chain are needed, thus making the scheme low-cost and efficient. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Secure scan design / Security / Testability / Design-for-test / Extended de Bruijn graph / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 431, DC2008-78, pp. 61-66, Feb. 2009. | |
| Paper # | DC2008-78 | |
| Date of Issue | 2009-02-09 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2008-78 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2009-02-16 - 2009-02-16 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2009-02-DC |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Secure Scan Design Approach using Extended de Bruijn Graph |
| Sub Title (in English) | |
| Keyword(1) | Secure scan design |
| Keyword(2) | Security |
| Keyword(3) | Testability |
| Keyword(4) | Design-for-test |
| Keyword(5) | Extended de Bruijn graph |
| Keyword(6) | |
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| 1st Author's Name | Hideo Fujiwara |
| 1st Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 2nd Author's Name | Marie Engelene J. Obien |
| 2nd Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
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| Speaker | Author-2 |
| Date Time | 2009-02-16 16:10:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2008-78 |
| Volume (vol) | vol.108 |
| Number (no) | no.431 |
| Page | pp.61-66 |
| #Pages | 6 |
| Date of Issue | 2009-02-09 (DC) |
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