Paper Abstract and Keywords |
Presentation |
2009-03-12 13:00
Emulation of Sequential Circuits by a Parallel Branching Program Machine Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Technology Corp.) VLD2008-145 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The parallel branching program machine~(PBM128) consists of 128 branching program machines~(BMs)
and a programmable interconnection.
To represent logic functions on BMs, we use quaternary decision diagrams.
To evaluate functions, we use 3-address quaternary branch instructions.
We realized many benchmark functions on PBM128,
and compared its memory size and computation time with the Intel's Core2Duo microprocessor.
PBM128 requires approximately quarter of the memory for the Core2Duo,
and is 21.4-96.1 times faster than the Core2Duo. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Embedded System / Branching Program Machine / Multi-Processing / BDD / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 478, VLD2008-145, pp. 111-116, March 2009. |
Paper # |
VLD2008-145 |
Date of Issue |
2009-03-04 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2008-145 |
Conference Information |
Committee |
VLD |
Conference Date |
2009-03-11 - 2009-03-13 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
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Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Technology for a System-on-Silicon |
Paper Information |
Registration To |
VLD |
Conference Code |
2009-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Emulation of Sequential Circuits by a Parallel Branching Program Machine |
Sub Title (in English) |
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Keyword(1) |
Embedded System |
Keyword(2) |
Branching Program Machine |
Keyword(3) |
Multi-Processing |
Keyword(4) |
BDD |
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1st Author's Name |
Hiroki Nakahara |
1st Author's Affiliation |
Kyushu Institute of Technology (Kyushu Inst. of Tech.) |
2nd Author's Name |
Tsutomu Sasao |
2nd Author's Affiliation |
Kyushu Institute of Technology (Kyushu Inst. of Tech.) |
3rd Author's Name |
Munehiro Matsuura |
3rd Author's Affiliation |
Kyushu Institute of Technology (Kyushu Inst. of Tech.) |
4th Author's Name |
Yoshifumi Kawamura |
4th Author's Affiliation |
Renesas Technology Corp. (Renesas Technology Corp.) |
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Speaker |
Author-1 |
Date Time |
2009-03-12 13:00:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2008-145 |
Volume (vol) |
vol.108 |
Number (no) |
no.478 |
Page |
pp.111-116 |
#Pages |
6 |
Date of Issue |
2009-03-04 (VLD) |
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