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Paper Abstract and Keywords
Presentation 2009-04-14 10:40
A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme
Shusuke Yoshimoto, Yusuke Iguchi, Shunsuke Okumura, Hidehiro Fujiwara, Hiroki Noguchi (Kobe Univ.), Koji Nii (Renesas Technology Corp.), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2009-6
Abstract (in Japanese) (See Japanese page) 
(in English) We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster access time and low voltage operation. The cell area is reduced by 25%, and the cell current is increased by 21%, compared with the prior 10T cell. The minimum operating voltage is lowered by the column line assist (CLA) scheme that suppresses write margin degradation. By measurement, we confirmed that the proposed 128-kb SRAM works at 0.56 V.
Keyword (in Japanese) (See Japanese page) 
(in English) SRAM / low voltage operation / small area / 10 transistor / 10T / Column line assist / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 2, ICD2009-6, pp. 27-32, April 2009.
Paper # ICD2009-6 
Date of Issue 2009-04-06 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2009-6

Conference Information
Committee ICD  
Conference Date 2009-04-13 - 2009-04-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Daikanso (Matsushima, Miyagi) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Semiconductor Memory Technologies 
Paper Information
Registration To ICD 
Conference Code 2009-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme 
Sub Title (in English)  
Keyword(1) SRAM  
Keyword(2) low voltage operation  
Keyword(3) small area  
Keyword(4) 10 transistor  
Keyword(5) 10T  
Keyword(6) Column line assist  
Keyword(7)  
Keyword(8)  
1st Author's Name Shusuke Yoshimoto  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name Yusuke Iguchi  
2nd Author's Affiliation Kobe University (Kobe Univ.)
3rd Author's Name Shunsuke Okumura  
3rd Author's Affiliation Kobe University (Kobe Univ.)
4th Author's Name Hidehiro Fujiwara  
4th Author's Affiliation Kobe University (Kobe Univ.)
5th Author's Name Hiroki Noguchi  
5th Author's Affiliation Kobe University (Kobe Univ.)
6th Author's Name Koji Nii  
6th Author's Affiliation Renesas Technology Corporation (Renesas Technology Corp.)
7th Author's Name Hiroshi Kawaguchi  
7th Author's Affiliation Kobe University (Kobe Univ.)
8th Author's Name Masahiko Yoshimoto  
8th Author's Affiliation Kobe University (Kobe Univ.)
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Speaker Author-1 
Date Time 2009-04-14 10:40:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2009-6 
Volume (vol) vol.109 
Number (no) no.2 
Page pp.27-32 
#Pages 6 
Date of Issue 2009-04-06 (ICD) 

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