Paper Abstract and Keywords |
Presentation |
2009-04-21 16:35
Pulse Propagation Analysis for SER Evaluation of Logic Circuits Shoji Harada, Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ) CPSY2009-9 DC2009-9 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
As a transistor feature size scales down in recent years, soft error tends to increase. In logic circuits, a pulse genarated at the output of a gate will cause an error if it propagates to a primary output or is latched into a memory element. When circuit designers consider soft error tolerance in circuit design, they must examine whether the circuit has desirable a soft error tolerance. Generally, Soft error rate(SER) is used as an index of such purpose. Computing SER needs pulse generation probability and pulse propagation probability. The latter is computed with pulse propagation analysis. It needs to consider maskings which block pulse propagation and Pulse Transformation(PT). Currently, most past methods do not consider PT in pulse propagation analysis and the methods sufficiently is considered the validity. In this paper, We estimate an impact of considering PT or not in pulse propagation analysis against SER compution accuracy. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
soft error / logic circuit / timing simulation / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 12, DC2009-9, pp. 49-54, April 2009. |
Paper # |
DC2009-9 |
Date of Issue |
2009-04-14 (CPSY, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CPSY2009-9 DC2009-9 |
Conference Information |
Committee |
DC CPSY |
Conference Date |
2009-04-21 - 2009-04-21 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Akihabara Satellite Campus, Tokyo Metropolitan Univ. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Dependable Computer Systems, Security Technology, etc. |
Paper Information |
Registration To |
DC |
Conference Code |
2009-04-DC-CPSY |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Pulse Propagation Analysis for SER Evaluation of Logic Circuits |
Sub Title (in English) |
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Keyword(1) |
soft error |
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logic circuit |
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timing simulation |
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1st Author's Name |
Shoji Harada |
1st Author's Affiliation |
Kyushu University (Kyushu Univ) |
2nd Author's Name |
Yusuke Akamine |
2nd Author's Affiliation |
Kyushu University (Kyushu Univ) |
3rd Author's Name |
Masayoshi Yoshimura |
3rd Author's Affiliation |
Kyushu University (Kyushu Univ) |
4th Author's Name |
Yusuke Matsunaga |
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Kyushu University (Kyushu Univ) |
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Speaker |
Author-1 |
Date Time |
2009-04-21 16:35:00 |
Presentation Time |
25 minutes |
Registration for |
DC |
Paper # |
CPSY2009-9, DC2009-9 |
Volume (vol) |
vol.109 |
Number (no) |
no.11(CPSY), no.12(DC) |
Page |
pp.49-54 |
#Pages |
6 |
Date of Issue |
2009-04-14 (CPSY, DC) |
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