講演抄録/キーワード |
講演名 |
2009-05-14 14:00
Performance and Cost Evaluations of On-Chip Network Topologies in FPGAs ○Sen In・Hiroki Matsutani・Daihang Wang(Keio Univ)・Michihiro Koibuchi(NII)・Hideharu Amano(Keio Univ) RECONF2009-3 |
抄録 |
(和) |
The on-chip interconnection network has been used to connect
many modules in reconfigurable systems, such as FPGAs,
The network topology is a crucial factor that affects the
performance and cost of the system, and various network
topologies have been proposed so far.
In this paper, we estimate the performance of 2-D mesh, 2-D
torus, fat trees, Spidergon, Concentrated mesh, and Flatten
butterfly by using a network simulator.
We synthesize these topologies in typical FPGAs and estimate
their cost, in order to reveal the cost-efficient on-chip
network structure in reconfigurable systems. |
(英) |
The on-chip interconnection network has been used to connect
many modules in reconfigurable systems, such as FPGAs,
The network topology is a crucial factor that affects the
performance and cost of the system, and various network
topologies have been proposed so far.
In this paper, we estimate the performance of 2-D mesh, 2-D
torus, fat trees, Spidergon, Concentrated mesh, and Flatten
butterfly by using a network simulator.
We synthesize these topologies in typical FPGAs and estimate
their cost, in order to reveal the cost-efficient on-chip
network structure in reconfigurable systems. |
キーワード |
(和) |
Network-on-Chip / Concentrated Mesh / k-ary n-cube / Spidergon / Fat-Tree / FPGA / Topology / |
(英) |
Network-on-Chip / Concentrated Mesh / k-ary n-cube / Spidergon / Fat-Tree / FPGA / Topology / |
文献情報 |
信学技報, vol. 109, no. 26, RECONF2009-3, pp. 13-18, 2009年5月. |
資料番号 |
RECONF2009-3 |
発行日 |
2009-05-07 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
RECONF2009-3 |
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