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Paper Abstract and Keywords
Presentation 2009-05-14 14:00
Performance and Cost Evaluations of On-Chip Network Topologies in FPGAs
Sen In, Hiroki Matsutani, Daihang Wang (Keio Univ), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ) RECONF2009-3
Abstract (in Japanese) (See Japanese page) 
(in English) The on-chip interconnection network has been used to connect
many modules in reconfigurable systems, such as FPGAs,
The network topology is a crucial factor that affects the
performance and cost of the system, and various network
topologies have been proposed so far.
In this paper, we estimate the performance of 2-D mesh, 2-D
torus, fat trees, Spidergon, Concentrated mesh, and Flatten
butterfly by using a network simulator.
We synthesize these topologies in typical FPGAs and estimate
their cost, in order to reveal the cost-efficient on-chip
network structure in reconfigurable systems.
Keyword (in Japanese) (See Japanese page) 
(in English) Network-on-Chip / Concentrated Mesh / k-ary n-cube / Spidergon / Fat-Tree / FPGA / Topology /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 26, RECONF2009-3, pp. 13-18, May 2009.
Paper # RECONF2009-3 
Date of Issue 2009-05-07 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2009-3

Conference Information
Committee RECONF  
Conference Date 2009-05-14 - 2009-05-15 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To RECONF 
Conference Code 2009-05-RECONF 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Performance and Cost Evaluations of On-Chip Network Topologies in FPGAs 
Sub Title (in English)  
Keyword(1) Network-on-Chip  
Keyword(2) Concentrated Mesh  
Keyword(3) k-ary n-cube  
Keyword(4) Spidergon  
Keyword(5) Fat-Tree  
Keyword(6) FPGA  
Keyword(7) Topology  
Keyword(8)  
1st Author's Name Sen In  
1st Author's Affiliation Keio University (Keio Univ)
2nd Author's Name Hiroki Matsutani  
2nd Author's Affiliation Keio University (Keio Univ)
3rd Author's Name Daihang Wang  
3rd Author's Affiliation Keio University (Keio Univ)
4th Author's Name Michihiro Koibuchi  
4th Author's Affiliation National Institute of Informatics (NII)
5th Author's Name Hideharu Amano  
5th Author's Affiliation Keio University (Keio Univ)
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Speaker Author-1 
Date Time 2009-05-14 14:00:00 
Presentation Time 30 minutes 
Registration for RECONF 
Paper # RECONF2009-3 
Volume (vol) vol.109 
Number (no) no.26 
Page pp.13-18 
#Pages 6 
Date of Issue 2009-05-07 (RECONF) 

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