Paper Abstract and Keywords |
Presentation |
2009-07-16 14:00
A 60pJ, 3-Clock Rising Time, VTH Loss Compensated Word-line Booster Circuit for 0.5V Power Supply Embedded/Discrete DRAMs Shuhei Tanakamaru, Ken Takeuchi (Univ. of Tokyo) SDM2009-103 ICD2009-19 Link to ES Tech. Rep. Archives: SDM2009-103 ICD2009-19 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A low power high-speed word-line booster is proposed for 0.5V operation DRAM. Word-line booster is composed of stand-by charge pump and active kicker. The active kicker is produced in this paper. Fast rising time is realized by utilizing switched-capacitor type booster. 3-clock rising time is achieved which is shorter than the entire DRAM access time. The rising time is 25% and the power consumption is 48% of the conventional circuits. With a fast and low power advantage, the proposed scheme is a promising candidate for the word-line booster of the future 0.5V operation DRAMs. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Charge-pump / DRAM / Word-line booster / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 134, ICD2009-19, pp. 33-38, July 2009. |
Paper # |
ICD2009-19 |
Date of Issue |
2009-07-09 (SDM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
SDM2009-103 ICD2009-19 Link to ES Tech. Rep. Archives: SDM2009-103 ICD2009-19 |
Conference Information |
Committee |
ICD SDM |
Conference Date |
2009-07-16 - 2009-07-17 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Tokyo Institute of Technology |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Low voltage/low power techniques, novel devices, circuits, and applications |
Paper Information |
Registration To |
ICD |
Conference Code |
2009-07-ICD-SDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A 60pJ, 3-Clock Rising Time, VTH Loss Compensated Word-line Booster Circuit for 0.5V Power Supply Embedded/Discrete DRAMs |
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Charge-pump |
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DRAM |
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Word-line booster |
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1st Author's Name |
Shuhei Tanakamaru |
1st Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
2nd Author's Name |
Ken Takeuchi |
2nd Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
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Speaker |
Author-1 |
Date Time |
2009-07-16 14:00:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
SDM2009-103, ICD2009-19 |
Volume (vol) |
vol.109 |
Number (no) |
no.133(SDM), no.134(ICD) |
Page |
pp.33-38 |
#Pages |
6 |
Date of Issue |
2009-07-09 (SDM, ICD) |
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