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Paper Abstract and Keywords
Presentation 2009-09-17 15:15
An analysis of frequency in the use LUT logic functions based on P-equivalence class
Masaki Shintani, Kota Kato, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2009-24
Abstract (in Japanese) (See Japanese page) 
(in English) Look-up table (LUT) has many SRAM and multiplexers, and you can implement any logic function to LUTs if the number of its input signals do not exceed the number of input ports. In other words, it may safely be said that LUT is the perfect logic cell which have ability to represent any logics. But, there might be the logic cell which are fewer than the number of both SRAMs and transistors of LUT. In this paper, we investigate the usage of logic functions by analyzing several benchmarks in order to develop an efficient logic cells. We consider the point that belong to P-equivalence class if permuting some of the input variables of function $g_1$ derives function $g_2$ from $g_1$. As a result, the number of logic functions in P-equivalence class is decreased about 60\% compared with all used logic functions.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / LUT / P-equivalence class / / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 198, RECONF2009-24, pp. 31-36, Sept. 2009.
Paper # RECONF2009-24 
Date of Issue 2009-09-10 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2009-24

Conference Information
Committee RECONF  
Conference Date 2009-09-17 - 2009-09-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Utsunomiya Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Sysytems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2009-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An analysis of frequency in the use LUT logic functions based on P-equivalence class 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) LUT  
Keyword(3) P-equivalence class  
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1st Author's Name Masaki Shintani  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Kota Kato  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Motoki Amagasaki  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Masahiro Iida  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Toshinori Sueyoshi  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker Author-1 
Date Time 2009-09-17 15:15:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2009-24 
Volume (vol) vol.109 
Number (no) no.198 
Page pp.31-36 
#Pages 6 
Date of Issue 2009-09-10 (RECONF) 

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