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Paper Abstract and Keywords
Presentation 2009-09-18 13:35
An Asynchronous FPGA Using LEDR/4-Phase-Dual-Rail Protocol Converters
Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2009-36
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents an asynchronous FPGA that combines the 4-phase dual-rail encoding and the Level-Encoded Dual-Rail (LEDR) encoding. The 4-phase dual-rail encoding is employed to achieve small area for function units, while the LEDR encoding is employed to achieve high throughput and low power for the data transfer using programmable interconnection resources. Area-efficient protocol converters are also proposed in transistor-level optimization. The proposed architecture is designed using a 90nm CMOS process. Compared to the 4-phase-dual-rail-based FPGA, the throughput and the power consumption are respectively by 45\% higher and by 36\% lower with almost the same transisitor count. Compared to the LEDR-based FPGA, the transistor count is by 35\% lower with almost the same power consumption.
Keyword (in Japanese) (See Japanese page) 
(in English) Reconfigurable VLSI / Field-programmable VLSI / LEDR (Level-Encoded Dual-Rail) encoding / 4-phase dual-rail encoding / Self-timed architecture / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 198, RECONF2009-36, pp. 103-108, Sept. 2009.
Paper # RECONF2009-36 
Date of Issue 2009-09-10 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2009-36

Conference Information
Committee RECONF  
Conference Date 2009-09-17 - 2009-09-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Utsunomiya Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Sysytems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2009-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Asynchronous FPGA Using LEDR/4-Phase-Dual-Rail Protocol Converters 
Sub Title (in English)  
Keyword(1) Reconfigurable VLSI  
Keyword(2) Field-programmable VLSI  
Keyword(3) LEDR (Level-Encoded Dual-Rail) encoding  
Keyword(4) 4-phase dual-rail encoding  
Keyword(5) Self-timed architecture  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Shota Ishihara  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Yoshiya Komatsu  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Masanori Hariyama  
3rd Author's Affiliation Tohoku University (Tohoku Univ.)
4th Author's Name Michitaka Kameyama  
4th Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker Author-1 
Date Time 2009-09-18 13:35:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2009-36 
Volume (vol) vol.109 
Number (no) no.198 
Page pp.103-108 
#Pages 6 
Date of Issue 2009-09-10 (RECONF) 

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