Paper Abstract and Keywords |
Presentation |
2009-10-01 10:00
Evaluation and Analysis of Substrate Noise in Microprocessor Yoji Bando (Kobe Univ.), Daisuke Kosaka (A-R-Tec), Goichi Yokomizo, Kunihiko Tsuboi (STARC), Ying Shiun Li, Shen Lin (Apache), Makoto Nagata (Kobe Univ./A-R-Tec) ICD2009-35 Link to ES Tech. Rep. Archives: ICD2009-35 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
An integrated power and substrate noise analysis environment targeting systems-on-chip (SoC) design was verified through comparison with on-chip noise measurements of a microprocessor chip in a 90-nm CMOS technology. The test chip includes 12 pairs of power and ground noise monitors within a processor and also embedds substrate noise evaluation areas with 120 probing points, realizing power and substrate noise measurements in terms of time-domain dynamic waveforms and spacial distribution. In addition to noise generation in digital circuits, noise propagation through on-chip silicon substrate and off-chip package and board impedances needs to be carefully considered for quantitative and quality power noise simulation. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
power noise / substrate noise / silicon correlation / on-chip noise monitor / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 214, ICD2009-35, pp. 11-14, Oct. 2009. |
Paper # |
ICD2009-35 |
Date of Issue |
2009-09-24 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2009-35 Link to ES Tech. Rep. Archives: ICD2009-35 |
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