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Paper Abstract and Keywords
Presentation 2009-10-01 10:00
Evaluation and Analysis of Substrate Noise in Microprocessor
Yoji Bando (Kobe Univ.), Daisuke Kosaka (A-R-Tec), Goichi Yokomizo, Kunihiko Tsuboi (STARC), Ying Shiun Li, Shen Lin (Apache), Makoto Nagata (Kobe Univ./A-R-Tec) ICD2009-35
Abstract (in Japanese) (See Japanese page) 
(in English) An integrated power and substrate noise analysis environment targeting systems-on-chip (SoC) design was verified through comparison with on-chip noise measurements of a microprocessor chip in a 90-nm CMOS technology. The test chip includes 12 pairs of power and ground noise monitors within a processor and also embedds substrate noise evaluation areas with 120 probing points, realizing power and substrate noise measurements in terms of time-domain dynamic waveforms and spacial distribution. In addition to noise generation in digital circuits, noise propagation through on-chip silicon substrate and off-chip package and board impedances needs to be carefully considered for quantitative and quality power noise simulation.
Keyword (in Japanese) (See Japanese page) 
(in English) power noise / substrate noise / silicon correlation / on-chip noise monitor / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 214, ICD2009-35, pp. 11-14, Oct. 2009.
Paper # ICD2009-35 
Date of Issue 2009-09-24 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2009-35

Conference Information
Committee ICD ITE-IST  
Conference Date 2009-10-01 - 2009-10-02 
Place (in Japanese) (See Japanese page) 
Place (in English) CIC Tokyo (Tamachi) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Analog, Mixed analog and digital, RF, and sensor interface circuitry 
Paper Information
Registration To ICD 
Conference Code 2009-10-ICD-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Evaluation and Analysis of Substrate Noise in Microprocessor 
Sub Title (in English)  
Keyword(1) power noise  
Keyword(2) substrate noise  
Keyword(3) silicon correlation  
Keyword(4) on-chip noise monitor  
Keyword(5)  
Keyword(6)  
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Keyword(8)  
1st Author's Name Yoji Bando  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name Daisuke Kosaka  
2nd Author's Affiliation A-R-Tec Corp. (A-R-Tec)
3rd Author's Name Goichi Yokomizo  
3rd Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
4th Author's Name Kunihiko Tsuboi  
4th Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
5th Author's Name Ying Shiun Li  
5th Author's Affiliation Apache Design Solutions (Apache)
6th Author's Name Shen Lin  
6th Author's Affiliation Apache Design Solutions (Apache)
7th Author's Name Makoto Nagata  
7th Author's Affiliation Kobe University/A-R-Tec Corp. (Kobe Univ./A-R-Tec)
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Speaker Author-1 
Date Time 2009-10-01 10:00:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2009-35 
Volume (vol) vol.109 
Number (no) no.214 
Page pp.11-14 
#Pages 4 
Date of Issue 2009-09-24 (ICD) 

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