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Paper Abstract and Keywords
Presentation 2009-12-02 15:40
Two-level Cache Simulation with L2 Unified Cache for Embedded Applications
Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-47 DC2009-34
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a two-level cache simulation method with L2 unified cache for embedded applications. It simulates L1 instruction cache, L1 data cache and L2 unified cache accurately in short period of time, by repeating simulation for L1/L2 instruction(data) cache several times. Additionally, by using several cache properties we can obtain the number of cache hits/misses whithout simulating several cache configurations. Our proposed approach totally runs a maximum of 3662.93 times faster than that of the conventional exhaustive approach.
Keyword (in Japanese) (See Japanese page) 
(in English) cache / unified cache / cache simulation / cache optimization / embedded system / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 315, VLD2009-47, pp. 37-42, Dec. 2009.
Paper # VLD2009-47 
Date of Issue 2009-11-25 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-47 DC2009-34

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2009-12-02 - 2009-12-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Kochi City Culture-Plaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2009 ―New Field of VLSI Design― 
Paper Information
Registration To VLD 
Conference Code 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Two-level Cache Simulation with L2 Unified Cache for Embedded Applications 
Sub Title (in English)  
Keyword(1) cache  
Keyword(2) unified cache  
Keyword(3) cache simulation  
Keyword(4) cache optimization  
Keyword(5) embedded system  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yuta Kobayashi  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Nozomu Togawa  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Masao Yanagisawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Tatsuo Ohtsuki  
4th Author's Affiliation Waseda University (Waseda Univ.)
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Speaker Author-1 
Date Time 2009-12-02 15:40:00 
Presentation Time 20 minutes 
Registration for VLD 
Paper # VLD2009-47, DC2009-34 
Volume (vol) vol.109 
Number (no) no.315(VLD), no.316(DC) 
Page pp.37-42 
#Pages 6 
Date of Issue 2009-11-25 (VLD, DC) 

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