Paper Abstract and Keywords |
Presentation |
2009-12-02 14:05
Multiplexer Minimization Based on Complete ILP Description of High-Level Synthesis Keisuke Inoue (JAIST/JSPS), Mineo Kaneko (JAIST) VLD2009-43 DC2009-30 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In high-level synthesis of LSI, it is an important task to minimize the number of connections between modules (functional units and registers), and the number and sizes of multiplexers as well as the length of schedule, the number of functional units and registers in terms of LSI chip area and operation performance. Recently, the authors have proposed an ILP description which executes simultaneously the three main tasks of high-level synthesis: scheduling, functional unit assignment, and register assignment. As an extension of this ILP description, this paper proposes an ILP-based treatment of connections between modules and multiplexers considering port assignment of functional units. The main contribution of this paper is to provide a general framework to minimize the number of connections, the number and sizes of multiplexers in cooperation with the adjustment of scheduling, functional unit assignment, register assignment, and port assignment of functional unit. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
High-level synthesis / Port assignment / Multiplexer minimization / Integer Linear Programming (ILP) / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 315, VLD2009-43, pp. 13-18, Dec. 2009. |
Paper # |
VLD2009-43 |
Date of Issue |
2009-11-25 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2009-43 DC2009-30 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2009-12-02 - 2009-12-04 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kochi City Culture-Plaza |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2009 ―New Field of VLSI Design― |
Paper Information |
Registration To |
VLD |
Conference Code |
2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Multiplexer Minimization Based on Complete ILP Description of High-Level Synthesis |
Sub Title (in English) |
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Keyword(1) |
High-level synthesis |
Keyword(2) |
Port assignment |
Keyword(3) |
Multiplexer minimization |
Keyword(4) |
Integer Linear Programming (ILP) |
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1st Author's Name |
Keisuke Inoue |
1st Author's Affiliation |
Japan Advanced Institute of Science and Technology/Japan Society for the Promotion of Science (JAIST/JSPS) |
2nd Author's Name |
Mineo Kaneko |
2nd Author's Affiliation |
Japan Advanced Institute of Science and Technology (JAIST) |
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Speaker |
Author-1 |
Date Time |
2009-12-02 14:05:00 |
Presentation Time |
20 minutes |
Registration for |
VLD |
Paper # |
VLD2009-43, DC2009-30 |
Volume (vol) |
vol.109 |
Number (no) |
no.315(VLD), no.316(DC) |
Page |
pp.13-18 |
#Pages |
6 |
Date of Issue |
2009-11-25 (VLD, DC) |
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