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Paper Abstract and Keywords
Presentation 2009-12-03 10:20
A Target Imedance of Power Distribution Network and LSI Packaging Design
Narimasa Takahashi, Yoshiyuki Kosaka, Masatoshi Ishii (IBM Japan), Makoto Shiroshita (KYOCERA SLC) CPM2009-144 ICD2009-73
Abstract (in Japanese) (See Japanese page) 
(in English) This paper describes the modeling analysis for a power distribution network and demonstrate co-design and co-simulation in using the detailed prototype model, which includes chip, package and printed circuit board. A circuit simulator and a 2D solver using the finite element method are used to study the frequency and transient responses for the core switching noise. In the model, we assume a chip model (current profile and on-chip capacitance) and define the circuit parameters with an equivalent circuit to meet the target impedance. Then the physical design of the package and printed circuit board were done to check all of the required circuit parameters. According to the modeling and evaluation, the package design with both the low equivalent series inductance capacitors and the low equivalent series resistance capacitors in the bottom layer with a thin core structure is more advantageous than a capacitor in the top layer.
Keyword (in Japanese) (See Japanese page) 
(in English) power distribution network / power integrity / target impedance / co-design / co-simulation / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 317, CPM2009-144, pp. 57-62, Dec. 2009.
Paper # CPM2009-144 
Date of Issue 2009-11-25 (CPM, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPM2009-144 ICD2009-73

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2009-12-02 - 2009-12-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Kochi City Culture-Plaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2009 ―New Field of VLSI Design― 
Paper Information
Registration To CPM 
Conference Code 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Target Imedance of Power Distribution Network and LSI Packaging Design 
Sub Title (in English)  
Keyword(1) power distribution network  
Keyword(2) power integrity  
Keyword(3) target impedance  
Keyword(4) co-design  
Keyword(5) co-simulation  
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1st Author's Name Narimasa Takahashi  
1st Author's Affiliation IBM Japan (IBM Japan)
2nd Author's Name Yoshiyuki Kosaka  
2nd Author's Affiliation IBM Japan (IBM Japan)
3rd Author's Name Masatoshi Ishii  
3rd Author's Affiliation IBM Japan (IBM Japan)
4th Author's Name Makoto Shiroshita  
4th Author's Affiliation KYOCERA SLC Technologies (KYOCERA SLC)
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Speaker Author-1 
Date Time 2009-12-03 10:20:00 
Presentation Time 20 minutes 
Registration for CPM 
Paper # CPM2009-144, ICD2009-73 
Volume (vol) vol.109 
Number (no) no.317(CPM), no.318(ICD) 
Page pp.57-62 
#Pages 6 
Date of Issue 2009-11-25 (CPM, ICD) 

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