Paper Abstract and Keywords |
Presentation |
2009-12-04 14:25
A Path Selection Method of Delay Test for Transistor Aging Mitsumasa Noda (Kyushu Institute of Tech.), Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Institute of Tech./JST), Yukiya Miura (Tokyo Metropolitan Univ./JST) VLD2009-65 DC2009-52 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
With the advanced VLSI process technology, it is important for reliability of VLSIs to deal with faults caused by aging. The speed of aging depends on not only the function of the circuit but also environment where the circuit is used. Hence detection of aging that would make a failure prefers to test on the field after shipping the VLSIs. This paper presents a method for selecting paths to be tested for delay degradation caused by NBTI under BIST-based self testing. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Aging / Negative Bias Temperature Instability / Delay Fault / Path Selection / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 316, DC2009-52, pp. 167-172, Dec. 2009. |
Paper # |
DC2009-52 |
Date of Issue |
2009-11-25 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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VLD2009-65 DC2009-52 |
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