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Paper Abstract and Keywords
Presentation 2009-12-04 14:25
A Path Selection Method of Delay Test for Transistor Aging
Mitsumasa Noda (Kyushu Institute of Tech.), Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Institute of Tech./JST), Yukiya Miura (Tokyo Metropolitan Univ./JST) VLD2009-65 DC2009-52
Abstract (in Japanese) (See Japanese page) 
(in English) With the advanced VLSI process technology, it is important for reliability of VLSIs to deal with faults caused by aging. The speed of aging depends on not only the function of the circuit but also environment where the circuit is used. Hence detection of aging that would make a failure prefers to test on the field after shipping the VLSIs. This paper presents a method for selecting paths to be tested for delay degradation caused by NBTI under BIST-based self testing.
Keyword (in Japanese) (See Japanese page) 
(in English) Aging / Negative Bias Temperature Instability / Delay Fault / Path Selection / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 316, DC2009-52, pp. 167-172, Dec. 2009.
Paper # DC2009-52 
Date of Issue 2009-11-25 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-65 DC2009-52

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2009-12-02 - 2009-12-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Kochi City Culture-Plaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2009 ―New Field of VLSI Design― 
Paper Information
Registration To DC 
Conference Code 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Path Selection Method of Delay Test for Transistor Aging 
Sub Title (in English)  
Keyword(1) Aging  
Keyword(2) Negative Bias Temperature Instability  
Keyword(3) Delay Fault  
Keyword(4) Path Selection  
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1st Author's Name Mitsumasa Noda  
1st Author's Affiliation Kyushu Institute of Technology (Kyushu Institute of Tech.)
2nd Author's Name Seiji Kajihara  
2nd Author's Affiliation Kyushu Institute of Technology/JST CREST (Kyushu Institute of Tech./JST)
3rd Author's Name Yasuo Sato  
3rd Author's Affiliation Kyushu Institute of Technology/JST CREST (Kyushu Institute of Tech./JST)
4th Author's Name Kohei Miyase  
4th Author's Affiliation Kyushu Institute of Technology/JST CREST (Kyushu Institute of Tech./JST)
5th Author's Name Xiaoqing Wen  
5th Author's Affiliation Kyushu Institute of Technology/JST CREST (Kyushu Institute of Tech./JST)
6th Author's Name Yukiya Miura  
6th Author's Affiliation Tokyo Metropolitan University/JST CREST (Tokyo Metropolitan Univ./JST)
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Speaker Author-1 
Date Time 2009-12-04 14:25:00 
Presentation Time 20 minutes 
Registration for DC 
Paper # VLD2009-65, DC2009-52 
Volume (vol) vol.109 
Number (no) no.315(VLD), no.316(DC) 
Page pp.167-172 
#Pages 6 
Date of Issue 2009-11-25 (VLD, DC) 

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