Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2009-12-04 10:20
Increasing Yield Using Partially-Programmable Circuits
Shigeru Yamashita (Ritsumeikan Univ.), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) VLD2009-59 DC2009-46
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes to use Partially-Programmable Circuits (PPCs) which are obtained from conventional logic circuits by replacing their sub-circuits with LUTs. If a connection in an PPC becomes redundant by changing the functionality of some LUTs, the connection is considered to be robust to defects because even if there are some defects at the connection, the circuit works properly by changing the functionality of some LUTs appropriately. To increase the number of such robust connections, we add some redundant connections to LUTs. We find such redundant connection by using functional flexibility represented by SPFDs and/or CSPFs. From the result of our preliminary experiments, we consider our approach is promising.
Keyword (in Japanese) (See Japanese page) 
(in English) yield / LUT / Partially-Programmable Circuit (PPC) / SPFD / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 315, VLD2009-59, pp. 125-130, Dec. 2009.
Paper # VLD2009-59 
Date of Issue 2009-11-25 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-59 DC2009-46

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2009-12-02 - 2009-12-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Kochi City Culture-Plaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2009 ―New Field of VLSI Design― 
Paper Information
Registration To VLD 
Conference Code 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Increasing Yield Using Partially-Programmable Circuits 
Sub Title (in English)  
Keyword(1) yield  
Keyword(2) LUT  
Keyword(3) Partially-Programmable Circuit (PPC)  
Keyword(4) SPFD  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Shigeru Yamashita  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
2nd Author's Name Hiroaki Yoshida  
2nd Author's Affiliation University of Tokyo (Univ. of Tokyo)
3rd Author's Name Masahiro Fujita  
3rd Author's Affiliation University of Tokyo (Univ. of Tokyo)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2009-12-04 10:20:00 
Presentation Time 20 minutes 
Registration for VLD 
Paper # VLD2009-59, DC2009-46 
Volume (vol) vol.109 
Number (no) no.315(VLD), no.316(DC) 
Page pp.125-130 
#Pages 6 
Date of Issue 2009-11-25 (VLD, DC) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan