Paper Abstract and Keywords |
Presentation |
2009-12-04 15:40
FlexMerge: A Logic Optimization Technique to Minimize Area for LUT-based FPGAs Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) VLD2009-68 DC2009-55 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents a novel logic optimization technique to minimize the number of LUTs for the post-processing of LUT-based FPGA technology mapping. The proposed method reduces the number of LUTs by merging two LUTs into an LUT using the don’t care of each LUTs without changing the functionality. The experimental results show that the proposed method reduces about 4% LUTs of LUT networks for MCNC benchmark set while the existing method reduces about 2% LUTs of LUT networks. The run-time of the proposed method, however, is about 6 times longer than the existing method. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
reconfigurable system / FPGA / logic synthesis / technology mapping / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 315, VLD2009-68, pp. 185-190, Dec. 2009. |
Paper # |
VLD2009-68 |
Date of Issue |
2009-11-25 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2009-68 DC2009-55 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2009-12-02 - 2009-12-04 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kochi City Culture-Plaza |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2009 ―New Field of VLSI Design― |
Paper Information |
Registration To |
VLD |
Conference Code |
2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
FlexMerge: A Logic Optimization Technique to Minimize Area for LUT-based FPGAs |
Sub Title (in English) |
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reconfigurable system |
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FPGA |
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logic synthesis |
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technology mapping |
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1st Author's Name |
Taiga Takata |
1st Author's Affiliation |
Kyushu University (Kyushu Univ.) |
2nd Author's Name |
Yusuke Matsunaga |
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Kyushu University (Kyushu Univ.) |
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Speaker |
Author-1 |
Date Time |
2009-12-04 15:40:00 |
Presentation Time |
20 minutes |
Registration for |
VLD |
Paper # |
VLD2009-68, DC2009-55 |
Volume (vol) |
vol.109 |
Number (no) |
no.315(VLD), no.316(DC) |
Page |
pp.185-190 |
#Pages |
6 |
Date of Issue |
2009-11-25 (VLD, DC) |
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