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Paper Abstract and Keywords
Presentation 2010-01-27 13:30
A Packet Classifier Using a Parallel Branching Program Machine
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Tech Corp.) VLD2009-92 CPSY2009-74 RECONF2009-77
Abstract (in Japanese) (See Japanese page) 
(in English) A branching program machine~(BM) is a special-purpose processor that
uses only two kinds of instructions: Branch and output instructions.
Thus, the architecture for the BM is much simpler than that for a general-purpose microprocessor~(MPU).
Since the BM uses the dedicated instructions for a special-purpose application,
it is faster than the MPU.
This paper presents a packet filter using a parallel BMs~(PBM).
To reduce computation time and code size,
first, a set of rules for packet filter is partitioned into subsets.
Then, the PBM evaluates them in parallel.
Also, the paper shows a method to estimate the necessary number of BMs to realize a given packet filter.
We implemented the PBM32, a system using 32 BMs, on an FPGA,
and compared it with the Intel's Core2Duo@1.2GHz microprocessor.
The PBM32 is 8.1-11.1 times faster than the Core2Duo,
and the PBM32 requries only 0.2-10.3 percent of the memory for the Core2Duo.
Keyword (in Japanese) (See Japanese page) 
(in English) Branching Program Machine / Packet Classifier / Embedded System / BDD / QDD / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 395, RECONF2009-77, pp. 143-148, Jan. 2010.
Paper # RECONF2009-77 
Date of Issue 2010-01-19 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-92 CPSY2009-74 RECONF2009-77

Conference Information
Committee IPSJ-SLDM VLD CPSY RECONF  
Conference Date 2010-01-26 - 2010-01-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Keio Univ (Hiyoshi Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2010-01-SLDM-VLD-CPSY-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Packet Classifier Using a Parallel Branching Program Machine 
Sub Title (in English)  
Keyword(1) Branching Program Machine  
Keyword(2) Packet Classifier  
Keyword(3) Embedded System  
Keyword(4) BDD  
Keyword(5) QDD  
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Keyword(7)  
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1st Author's Name Hiroki Nakahara  
1st Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
2nd Author's Name Tsutomu Sasao  
2nd Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
3rd Author's Name Munehiro Matsuura  
3rd Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
4th Author's Name Yoshifumi Kawamura  
4th Author's Affiliation Renesas Technology Corporation. (Renesas Tech Corp.)
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Speaker Author-1 
Date Time 2010-01-27 13:30:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2009-92, CPSY2009-74, RECONF2009-77 
Volume (vol) vol.109 
Number (no) no.393(VLD), no.394(CPSY), no.395(RECONF) 
Page pp.143-148 
#Pages 6 
Date of Issue 2010-01-19 (VLD, CPSY, RECONF) 

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