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Paper Abstract and Keywords
Presentation 2010-02-05 13:30
Optimization of Metallization Processes for 32-nm node Highly Reliable Ultralow-k (k=2.4)/Cu Multilevel Interconnects Incorporating a Bilayer Low-k Barrier Cap (k=3.9)
M. Iguchi, S. Yokogawa, Hirokazu Aizawa, Y. Kakuhara, Hideaki Tsuchiya, Norio Okada, Kiyotaka Imai, M. Tohara, K. Fujii (NEC Electronics), T. Watanabe (Toshiba) SDM2009-186
Abstract (in Japanese) (See Japanese page) 
(in English) Reliability of 32-nm-node ultralow-k (k=2.4)/Cu multilevel interconnects incorporating a bilayer low-k barrier cap (k=3.9) was improved without excessive wiring resistance by using CuAl seed technology with high-temperature and short-time annealing. Though the increase in wiring resistivity was about 10 %, both electromigration (EM) and stress-induced voiding (SiV) reliability was clearly improved by using Cu-0.5wt%Al seed metal.
Keyword (in Japanese) (See Japanese page) 
(in English) low-k interlayer dielectric / CuAl alloy seed process / Al segregation / Electromigration / Stress induced voiding / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 412, SDM2009-186, pp. 25-29, Feb. 2010.
Paper # SDM2009-186 
Date of Issue 2010-01-29 (SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2009-186

Conference Information
Committee SDM  
Conference Date 2010-02-05 - 2010-02-05 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SDM 
Conference Code 2010-02-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Optimization of Metallization Processes for 32-nm node Highly Reliable Ultralow-k (k=2.4)/Cu Multilevel Interconnects Incorporating a Bilayer Low-k Barrier Cap (k=3.9) 
Sub Title (in English)  
Keyword(1) low-k interlayer dielectric  
Keyword(2) CuAl alloy seed process  
Keyword(3) Al segregation  
Keyword(4) Electromigration  
Keyword(5) Stress induced voiding  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name M. Iguchi  
1st Author's Affiliation NEC Electronics Corporation (NEC Electronics)
2nd Author's Name S. Yokogawa  
2nd Author's Affiliation NEC Electronics Corporation (NEC Electronics)
3rd Author's Name Hirokazu Aizawa  
3rd Author's Affiliation NEC Electronics Corporation (NEC Electronics)
4th Author's Name Y. Kakuhara  
4th Author's Affiliation NEC Electronics Corporation (NEC Electronics)
5th Author's Name Hideaki Tsuchiya  
5th Author's Affiliation NEC Electronics Corporation (NEC Electronics)
6th Author's Name Norio Okada  
6th Author's Affiliation NEC Electronics Corporation (NEC Electronics)
7th Author's Name Kiyotaka Imai  
7th Author's Affiliation NEC Electronics Corporation (NEC Electronics)
8th Author's Name M. Tohara  
8th Author's Affiliation NEC Electronics Corporation (NEC Electronics)
9th Author's Name K. Fujii  
9th Author's Affiliation NEC Electronics Corporation (NEC Electronics)
10th Author's Name T. Watanabe  
10th Author's Affiliation Toshiba Corporation (Toshiba)
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Speaker Author-1 
Date Time 2010-02-05 13:30:00 
Presentation Time 30 minutes 
Registration for SDM 
Paper # SDM2009-186 
Volume (vol) vol.109 
Number (no) no.412 
Page pp.25-29 
#Pages 5 
Date of Issue 2010-01-29 (SDM) 

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