Paper Abstract and Keywords |
Presentation |
2010-02-05 13:30
Optimization of Metallization Processes for 32-nm node Highly Reliable Ultralow-k (k=2.4)/Cu Multilevel Interconnects Incorporating a Bilayer Low-k Barrier Cap (k=3.9) M. Iguchi, S. Yokogawa, Hirokazu Aizawa, Y. Kakuhara, Hideaki Tsuchiya, Norio Okada, Kiyotaka Imai, M. Tohara, K. Fujii (NEC Electronics), T. Watanabe (Toshiba) SDM2009-186 Link to ES Tech. Rep. Archives: SDM2009-186 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Reliability of 32-nm-node ultralow-k (k=2.4)/Cu multilevel interconnects incorporating a bilayer low-k barrier cap (k=3.9) was improved without excessive wiring resistance by using CuAl seed technology with high-temperature and short-time annealing. Though the increase in wiring resistivity was about 10 %, both electromigration (EM) and stress-induced voiding (SiV) reliability was clearly improved by using Cu-0.5wt%Al seed metal. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
low-k interlayer dielectric / CuAl alloy seed process / Al segregation / Electromigration / Stress induced voiding / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 412, SDM2009-186, pp. 25-29, Feb. 2010. |
Paper # |
SDM2009-186 |
Date of Issue |
2010-01-29 (SDM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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SDM2009-186 Link to ES Tech. Rep. Archives: SDM2009-186 |