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| Presentation | 2010-02-05 11:20 Feasibility Study of 70nm Pitch Cu/Porous Low-k D/D Integration Featuring EUV Lithography toward 22nm Generation Naofumi Nakamura, Noriaki Oda, Eiichi Soda, Nobuki Hosoi, Akifumi Gawase, Hajime Aoyama, Y. Tanaka, D. Kawamura, S. Chikaki, M. Shiohara, Nobuaki Tarumi, S. Kondo, Ichiro Mori, S. Saito (SELETE)  SDM2009-184 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A feasibility study of 70 nm pitch 2-level dual damascene interconnects featuring EUV lithography is presented. Using Ru barrier metal and scalable porous silica (Po-SiO, k=2.1), a low resistivity below 4.5 uOhmcm and a 13 % reduction in wiring capacitance compared with porous SiOC (k=2.65) was obtained. The predicted circuit- performance using Po-SiO was 10 % higher than that with porous SiOC. The electromigration reliability in 22 nm generation was consistent with the previous generations. The merit of EUV lithography on circuit design was also clarified. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | 70nm pitch wiring / EUV lithography / CF3I etching gas / PVD-Ru / Porous-Silica / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 412, SDM2009-184, pp. 13-18, Feb. 2010. | |
| Paper # | SDM2009-184 | |
| Date of Issue | 2010-01-29 (SDM) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2009-184 |
|
| Conference Information | |
| Committee | SDM |
| Conference Date | 2010-02-05 - 2010-02-05 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | SDM |
| Conference Code | 2010-02-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Feasibility Study of 70nm Pitch Cu/Porous Low-k D/D Integration Featuring EUV Lithography toward 22nm Generation |
| Sub Title (in English) | |
| Keyword(1) | 70nm pitch wiring |
| Keyword(2) | EUV lithography |
| Keyword(3) | CF3I etching gas |
| Keyword(4) | PVD-Ru |
| Keyword(5) | Porous-Silica |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Naofumi Nakamura |
| 1st Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. (SELETE) |
| 2nd Author's Name | Noriaki Oda |
| 2nd Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. (SELETE) |
| 3rd Author's Name | Eiichi Soda |
| 3rd Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. (SELETE) |
| 4th Author's Name | Nobuki Hosoi |
| 4th Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. (SELETE) |
| 5th Author's Name | Akifumi Gawase |
| 5th Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. (SELETE) |
| 6th Author's Name | Hajime Aoyama |
| 6th Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. (SELETE) |
| 7th Author's Name | Y. Tanaka |
| 7th Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. (SELETE) |
| 8th Author's Name | D. Kawamura |
| 8th Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. (SELETE) |
| 9th Author's Name | S. Chikaki |
| 9th Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. (SELETE) |
| 10th Author's Name | M. Shiohara |
| 10th Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. (SELETE) |
| 11th Author's Name | Nobuaki Tarumi |
| 11th Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. (SELETE) |
| 12th Author's Name | S. Kondo |
| 12th Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. (SELETE) |
| 13th Author's Name | Ichiro Mori |
| 13th Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. (SELETE) |
| 14th Author's Name | S. Saito |
| 14th Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. (SELETE) |
| Speaker | Author-1 |
| Date Time | 2010-02-05 11:20:00 |
| Presentation Time | 30 minutes |
| Registration for | SDM |
| Paper # | SDM2009-184 |
| Volume (vol) | vol.109 |
| Number (no) | no.412 |
| Page | pp.13-18 |
| #Pages | 6 |
| Date of Issue | 2010-01-29 (SDM) |
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