Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2010-02-15 16:05
Consideration of Open Faults Model Based on Digital Measurement of TEG Chip
Toshiyuki Tsutsumi (Meiji Univ.), Yasuyuki Kariya, Koji Yamazaki (Meiji Univ), Masaki Hashizume, Hiroyuki Yotsuyanagi (Tokushima Univ), Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu (Ehime Univ) DC2009-77
Abstract (in Japanese) (See Japanese page) 
(in English) Countermeasures against an open fault in LSI testing become more important with advancement of LSI process technology. However, a practicable modeling of the open fault has not been performed yet. So, we have fabricated TEG (Test Element Group) chips into which open defects is intentionally built, and then we research on modeling the open fault based on the measurement data of the TEG chips. In this paper, modeling of the open fault is considered. A technique to calculate the influence of adjacent lines on the faulty line based on digital measurement data of the TEG chips using RCGA(Real-Coded Genetic Algorithm) is proposed. The proposed model based on the digital measurement using RCGA can mostly simulate the logical value of the line with open fault, and shows high quality without considering the interconnect structure. Moreover, we attempt to simplify the model by averaging the influence of adjacent lines, and the simplification shows effectiveness.
Keyword (in Japanese) (See Japanese page) 
(in English) open faults / TEG chip / fault model / LSI testing / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 416, DC2009-77, pp. 75-80, Feb. 2010.
Paper # DC2009-77 
Date of Issue 2010-02-08 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF DC2009-77

Conference Information
Committee DC  
Conference Date 2010-02-15 - 2010-02-15 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2010-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Consideration of Open Faults Model Based on Digital Measurement of TEG Chip 
Sub Title (in English)  
Keyword(1) open faults  
Keyword(2) TEG chip  
Keyword(3) fault model  
Keyword(4) LSI testing  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Toshiyuki Tsutsumi  
1st Author's Affiliation Meiji University (Meiji Univ.)
2nd Author's Name Yasuyuki Kariya  
2nd Author's Affiliation Meiji University (Meiji Univ)
3rd Author's Name Koji Yamazaki  
3rd Author's Affiliation Meiji University (Meiji Univ)
4th Author's Name Masaki Hashizume  
4th Author's Affiliation Tokushima University (Tokushima Univ)
5th Author's Name Hiroyuki Yotsuyanagi  
5th Author's Affiliation Tokushima University (Tokushima Univ)
6th Author's Name Hiroshi Takahashi  
6th Author's Affiliation Ehime University (Ehime Univ)
7th Author's Name Yoshinobu Higami  
7th Author's Affiliation Ehime University (Ehime Univ)
8th Author's Name Yuzo Takamatsu  
8th Author's Affiliation Ehime University (Ehime Univ)
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-2 
Date Time 2010-02-15 16:05:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2009-77 
Volume (vol) vol.109 
Number (no) no.416 
Page pp.75-80 
#Pages 6 
Date of Issue 2010-02-08 (DC) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan