Paper Abstract and Keywords |
Presentation |
2010-02-15 16:05
Consideration of Open Faults Model Based on Digital Measurement of TEG Chip Toshiyuki Tsutsumi (Meiji Univ.), Yasuyuki Kariya, Koji Yamazaki (Meiji Univ), Masaki Hashizume, Hiroyuki Yotsuyanagi (Tokushima Univ), Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu (Ehime Univ) DC2009-77 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Countermeasures against an open fault in LSI testing become more important with advancement of LSI process technology. However, a practicable modeling of the open fault has not been performed yet. So, we have fabricated TEG (Test Element Group) chips into which open defects is intentionally built, and then we research on modeling the open fault based on the measurement data of the TEG chips. In this paper, modeling of the open fault is considered. A technique to calculate the influence of adjacent lines on the faulty line based on digital measurement data of the TEG chips using RCGA(Real-Coded Genetic Algorithm) is proposed. The proposed model based on the digital measurement using RCGA can mostly simulate the logical value of the line with open fault, and shows high quality without considering the interconnect structure. Moreover, we attempt to simplify the model by averaging the influence of adjacent lines, and the simplification shows effectiveness. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
open faults / TEG chip / fault model / LSI testing / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 416, DC2009-77, pp. 75-80, Feb. 2010. |
Paper # |
DC2009-77 |
Date of Issue |
2010-02-08 (DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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DC2009-77 |
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