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Paper Abstract and Keywords
Presentation 2010-02-15 16:05
Consideration of Open Faults Model Based on Digital Measurement of TEG Chip
Toshiyuki Tsutsumi (Meiji Univ.), Yasuyuki Kariya, Koji Yamazaki (Meiji Univ), Masaki Hashizume, Hiroyuki Yotsuyanagi (Tokushima Univ), Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu (Ehime Univ) DC2009-77
Abstract (in Japanese) (See Japanese page) 
(in English) Countermeasures against an open fault in LSI testing become more important with advancement of LSI process technology. However, a practicable modeling of the open fault has not been performed yet. So, we have fabricated TEG (Test Element Group) chips into which open defects is intentionally built, and then we research on modeling the open fault based on the measurement data of the TEG chips. In this paper, modeling of the open fault is considered. A technique to calculate the influence of adjacent lines on the faulty line based on digital measurement data of the TEG chips using RCGA(Real-Coded Genetic Algorithm) is proposed. The proposed model based on the digital measurement using RCGA can mostly simulate the logical value of the line with open fault, and shows high quality without considering the interconnect structure. Moreover, we attempt to simplify the model by averaging the influence of adjacent lines, and the simplification shows effectiveness.
Keyword (in Japanese) (See Japanese page) 
(in English) open faults / TEG chip / fault model / LSI testing / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 416, DC2009-77, pp. 75-80, Feb. 2010.
Paper # DC2009-77 
Date of Issue 2010-02-08 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2010-02-15 - 2010-02-15 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2010-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Consideration of Open Faults Model Based on Digital Measurement of TEG Chip 
Sub Title (in English)  
Keyword(1) open faults  
Keyword(2) TEG chip  
Keyword(3) fault model  
Keyword(4) LSI testing  
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1st Author's Name Toshiyuki Tsutsumi  
1st Author's Affiliation Meiji University (Meiji Univ.)
2nd Author's Name Yasuyuki Kariya  
2nd Author's Affiliation Meiji University (Meiji Univ)
3rd Author's Name Koji Yamazaki  
3rd Author's Affiliation Meiji University (Meiji Univ)
4th Author's Name Masaki Hashizume  
4th Author's Affiliation Tokushima University (Tokushima Univ)
5th Author's Name Hiroyuki Yotsuyanagi  
5th Author's Affiliation Tokushima University (Tokushima Univ)
6th Author's Name Hiroshi Takahashi  
6th Author's Affiliation Ehime University (Ehime Univ)
7th Author's Name Yoshinobu Higami  
7th Author's Affiliation Ehime University (Ehime Univ)
8th Author's Name Yuzo Takamatsu  
8th Author's Affiliation Ehime University (Ehime Univ)
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Speaker Author-2 
Date Time 2010-02-15 16:05:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2009-77 
Volume (vol) vol.109 
Number (no) no.416 
Page pp.75-80 
#Pages
Date of Issue 2010-02-08 (DC) 


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