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Paper Abstract and Keywords
Presentation 2010-02-15 10:25
Modeling resistive open faults and generating their tests
Hiroshi Takahashi, Yoshinobu Higami, Yuta Shudo, Yuji Takamune, Yuzo Takamatsu (Ehime Univ.), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) DC2009-68
Abstract (in Japanese) (See Japanese page) 
(in English) In order to solve the problem of signal integrity, we propose an extended delay fault model for modeling a resistive open fault.
We use the three-dimensional electromagnetic software to analyze the behavior of a line with the resistive open.
Under the extended delay fault model proposed in this paper, the size of the additional delay is depended on the signal transitions at the adjacent lines that are assigned by the test-pair.
Under the launch on capture (LOC) test, we propose a method for generating the test-pairs for the resistive open faults by using the transition fault tests with don't cares.
We demonstrated the experimental results to show that the proposed method is able to generate the test-pair for resistive open faults that cannot be detected by the given test-pairs for the transition faults.
Keyword (in Japanese) (See Japanese page) 
(in English) resistive open fault / test pattern generation / extended delay fault model / adjacent lines / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 416, DC2009-68, pp. 19-24, Feb. 2010.
Paper # DC2009-68 
Date of Issue 2010-02-08 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2010-02-15 - 2010-02-15 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2010-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Modeling resistive open faults and generating their tests 
Sub Title (in English)  
Keyword(1) resistive open fault  
Keyword(2) test pattern generation  
Keyword(3) extended delay fault model  
Keyword(4) adjacent lines  
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1st Author's Name Hiroshi Takahashi  
1st Author's Affiliation Ehime University (Ehime Univ.)
2nd Author's Name Yoshinobu Higami  
2nd Author's Affiliation Ehime University (Ehime Univ.)
3rd Author's Name Yuta Shudo  
3rd Author's Affiliation Ehime University (Ehime Univ.)
4th Author's Name Yuji Takamune  
4th Author's Affiliation Ehime University (Ehime Univ.)
5th Author's Name Yuzo Takamatsu  
5th Author's Affiliation Ehime University (Ehime Univ.)
6th Author's Name Toshiyuki Tsutsumi  
6th Author's Affiliation Meiji University (Meiji Univ.)
7th Author's Name Koji Yamazaki  
7th Author's Affiliation Meiji University (Meiji Univ.)
8th Author's Name Hiroyuki Yotsuyanagi  
8th Author's Affiliation The University of Tokushima (Univ. of Tokushima)
9th Author's Name Masaki Hashizume  
9th Author's Affiliation The University of Tokushima (Univ. of Tokushima)
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Speaker Author-1 
Date Time 2010-02-15 10:25:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2009-68 
Volume (vol) vol.109 
Number (no) no.416 
Page pp.19-24 
#Pages 6 
Date of Issue 2010-02-08 (DC) 

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