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Paper Abstract and Keywords
Presentation 2010-03-02 09:20
Preprocessing Method based on Operation Instruction Clustering of Code Optimization for a Processor Architecture with Bypass Chain
Yuki Kamada, Toshihiro Shoji, Jin Tian, Nobuhiko Sugino (Tokyou Inst. of Tech.) CAS2009-108 SIP2009-153 CS2009-103
Abstract (in Japanese) (See Japanese page) 
(in English) For a processor with a bypass chain, a novel code optimization method based on data flow graph (DFG) form is discussed. In order to utilize the bypass chain effectively, a post-pass code rescheduling method for a given DFG has been presented. There exist, however, large numbers of equivalent DFGs of alternative computational orders. In this article, a preprocessing method based on a clustering technique for associative and commutative operations is discussed, so that an equivalent DFG of lower parallelism is derived. The proposed method is applied to the existing code optimization method, and the results derived for several example programs show its effectiveness.
Keyword (in Japanese) (See Japanese page) 
(in English) Processor with Bypass network / Code Optimization / Low Power Consumption / / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 434, CAS2009-108, pp. 173-178, March 2010.
Paper # CAS2009-108 
Date of Issue 2010-02-22 (CAS, SIP, CS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2009-108 SIP2009-153 CS2009-103

Conference Information
Committee SIP CAS CS  
Conference Date 2010-03-01 - 2010-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Hotel Breeze Bay Marina, Miyakojima 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Signal processing for networking and communications, and others 
Paper Information
Registration To CAS 
Conference Code 2010-03-SIP-CAS-CS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Preprocessing Method based on Operation Instruction Clustering of Code Optimization for a Processor Architecture with Bypass Chain 
Sub Title (in English)  
Keyword(1) Processor with Bypass network  
Keyword(2) Code Optimization  
Keyword(3) Low Power Consumption  
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1st Author's Name Yuki Kamada  
1st Author's Affiliation Tokyou Institute of Technology (Tokyou Inst. of Tech.)
2nd Author's Name Toshihiro Shoji  
2nd Author's Affiliation Tokyou Institute of Technology (Tokyou Inst. of Tech.)
3rd Author's Name Jin Tian  
3rd Author's Affiliation Tokyou Institute of Technology (Tokyou Inst. of Tech.)
4th Author's Name Nobuhiko Sugino  
4th Author's Affiliation Tokyou Institute of Technology (Tokyou Inst. of Tech.)
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Speaker Author-1 
Date Time 2010-03-02 09:20:00 
Presentation Time 20 minutes 
Registration for CAS 
Paper # CAS2009-108, SIP2009-153, CS2009-103 
Volume (vol) vol.109 
Number (no) no.434(CAS), no.435(SIP), no.436(CS) 
Page pp.173-178 
#Pages 6 
Date of Issue 2010-02-22 (CAS, SIP, CS) 

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