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Paper Abstract and Keywords
Presentation 2010-03-04 17:25
An RSA Encryption Hardware Algorithm that uses a DSP block on the FPGA
Kensuke Kawakami, Koji Nakano (Hiroshima Univ.) IT2009-80 ISEC2009-88 WBS2009-59
Abstract (in Japanese) (See Japanese page) 
(in English) The main contribution of this paper is to present an efficient hardware algorithm for modular exponentiation, which is a key operation of RSA encryption/decryption. Our hardware algorithm is designed to be implemented in on the Xilinx Virtex-5 family FPGA XC5VSX50T-1, which has embedded DSP blocks (DSP48E) and embedded memory blocks (BRAM). In particular, our hardware algorithm efficiently uses these two embedded blocks such that it uses only one DSP48E block and one Block RAM for 1024-bit modular exponentiation. The implementation results showed that it runs run in no more than 44.8ms and in expected 33.8ms for 1024-bit modular exponentiation. Since it uses only one DSP48E block and one Block RAM, the FPGA can implement a lot of circuits which perform modulo exponentiation in parallel, in the same time.
Keyword (in Japanese) (See Japanese page) 
(in English) Modular Exponentiation / Montgomery multiplication / FPGA / RSA encryption/decription / DSP block / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 445, ISEC2009-88, pp. 61-68, March 2010.
Paper # ISEC2009-88 
Date of Issue 2010-02-25 (IT, ISEC, WBS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF IT2009-80 ISEC2009-88 WBS2009-59

Conference Information
Committee IT ISEC WBS  
Conference Date 2010-03-04 - 2010-03-05 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagano-Engineering Campus, Shinshu University 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ISEC 
Conference Code 2010-03-IT-ISEC-WBS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An RSA Encryption Hardware Algorithm that uses a DSP block on the FPGA 
Sub Title (in English)  
Keyword(1) Modular Exponentiation  
Keyword(2) Montgomery multiplication  
Keyword(3) FPGA  
Keyword(4) RSA encryption/decription  
Keyword(5) DSP block  
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Keyword(7)  
Keyword(8)  
1st Author's Name Kensuke Kawakami  
1st Author's Affiliation Hiroshima University (Hiroshima Univ.)
2nd Author's Name Koji Nakano  
2nd Author's Affiliation Hiroshima University (Hiroshima Univ.)
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Speaker Author-1 
Date Time 2010-03-04 17:25:00 
Presentation Time 25 minutes 
Registration for ISEC 
Paper # IT2009-80, ISEC2009-88, WBS2009-59 
Volume (vol) vol.109 
Number (no) no.444(IT), no.445(ISEC), no.446(WBS) 
Page pp.61-68 
#Pages 8 
Date of Issue 2010-02-25 (IT, ISEC, WBS) 

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