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Paper Abstract and Keywords
Presentation 2010-03-05 14:00
10Gbps implementation of TLS/SSL accelerator on FPGA
Takashi Isobe, Satoshi Tsutsumi (Hitachi Ltd.,), Koichiro Seto, Kenji Aoshima, Kazutoshi Kariya (Hitachi Cable Ltd.,) NS2009-260
Abstract (in Japanese) (See Japanese page) 
(in English) This paper is the one-chip architecture to mount all processes for TLS/SSL encrypted communication into one FPGA or ASIC, and shows the 10Gbps implementation of low-power (23W) TLS/SSL accelerator on 65nm FPGA. The usage of FPGA or ASIC enables high efficient processing parallelized, pipelined, and optimized in processing unit, and achieves low-power consumption. On-chip architecture enables the usage of switch to avoid the congestion in exchanging data between multi processing blocks, and enhances the throughput. In this research, to implement one-chip architecture, high-efficient processing (parallel processing shared with multi data, and a circuit shared for transmitting and receiving) decreased circuit area. In addition, to enhance the operating frequency, a switch downsized by sharing port for data exchange with multi blocks decreased the number of wires. By means of these techniques, circuit area to implement all TLS/SSL processes was reduced to less than that of 65nm FPGA used in this research, and 166MHz operating frequency required to realize 10Gbps throughput at 64-bit pipeline was achieved. In experimental evaluation using prototype, 23W power consumption and 10Gbps encryption throughput were achieved.
Keyword (in Japanese) (See Japanese page) 
(in English) TLS / SSL / Accelerator / SHA1 / RSA / AES / RC4 / MD5  
Reference Info. IEICE Tech. Rep., vol. 109, no. 448, NS2009-260, pp. 549-554, March 2010.
Paper # NS2009-260 
Date of Issue 2010-02-25 (NS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF NS2009-260

Conference Information
Committee NS IN  
Conference Date 2010-03-04 - 2010-03-05 
Place (in Japanese) (See Japanese page) 
Place (in English) Miyazaki Phoenix Seagaia Resort (Miyazaki) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) General, NS+IN workshop (March 4-5) 
Paper Information
Registration To NS 
Conference Code 2010-03-NS-IN 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) 10Gbps implementation of TLS/SSL accelerator on FPGA 
Sub Title (in English)  
Keyword(1) TLS  
Keyword(2) SSL  
Keyword(3) Accelerator  
Keyword(4) SHA1  
Keyword(5) RSA  
Keyword(6) AES  
Keyword(7) RC4  
Keyword(8) MD5  
1st Author's Name Takashi Isobe  
1st Author's Affiliation Hitachi, Limited., Central Research Laboratory (Hitachi Ltd.,)
2nd Author's Name Satoshi Tsutsumi  
2nd Author's Affiliation Hitachi, Limited., Central Research Laboratory (Hitachi Ltd.,)
3rd Author's Name Koichiro Seto  
3rd Author's Affiliation Hitachi Cable, Limited., (Hitachi Cable Ltd.,)
4th Author's Name Kenji Aoshima  
4th Author's Affiliation Hitachi Cable, Limited., (Hitachi Cable Ltd.,)
5th Author's Name Kazutoshi Kariya  
5th Author's Affiliation Hitachi Cable, Limited., (Hitachi Cable Ltd.,)
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Speaker Author-1 
Date Time 2010-03-05 14:00:00 
Presentation Time 20 minutes 
Registration for NS 
Paper # NS2009-260 
Volume (vol) vol.109 
Number (no) no.448 
Page pp.549-554 
#Pages
Date of Issue 2010-02-25 (NS) 


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