Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2010-03-10 15:50
Variation-Tolerant Decomposition of MOS Transistor
Bo Liu, Atsushi Ochi, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2009-104
Abstract (in Japanese) (See Japanese page) 
(in English) Aiming at the layout automation based on the regular bulk structure
in MOS analog circuits, we study how to decompose a MOS transistor into unit-transistors with the short channel width and length. We developed the TEG (Test Element Group) on $90nm$ manufacturing process where various transistors decomposed with respect to channel length/width and diffusion sharing/isolation. Evaluating the DC characteristics of the transistors in the TEG as well as focusing the manufacturing variation, we provide guidelines for the channel decomposition to suppress the manufacturing variation taking the layout area into account.
Keyword (in Japanese) (See Japanese page) 
(in English) MOS analog layout / egular bulk structure / manufacturing variation / channel decomposition / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 462, VLD2009-104, pp. 31-36, March 2010.
Paper # VLD2009-104 
Date of Issue 2010-03-03 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-104

Conference Information
Committee VLD  
Conference Date 2010-03-10 - 2010-03-12 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2010-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Variation-Tolerant Decomposition of MOS Transistor 
Sub Title (in English)  
Keyword(1) MOS analog layout  
Keyword(2) egular bulk structure  
Keyword(3) manufacturing variation  
Keyword(4) channel decomposition  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Bo Liu  
1st Author's Affiliation The University of Kitakyushu (Univ. of Kitakyushu)
2nd Author's Name Atsushi Ochi  
2nd Author's Affiliation The University of Kitakyushu (Univ. of Kitakyushu)
3rd Author's Name Shigetoshi Nakatake  
3rd Author's Affiliation The University of Kitakyushu (Univ. of Kitakyushu)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2010-03-10 15:50:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2009-104 
Volume (vol) vol.109 
Number (no) no.462 
Page pp.31-36 
#Pages 6 
Date of Issue 2010-03-03 (VLD) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan