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Paper Abstract and Keywords
Presentation 2010-03-11 10:50
Wiring delay of Logic Element used in Via programmable logic device VPEX
Tomohiro Nishimoto, Tatsuya Kitamori, Yuuichi Kokushou, Shouta Yamada (Ritsumeikan Univ), Masaya Yoshikawa (Meijou Univ), Takeshi Fujino (Ritsumeikan Univ) VLD2009-109
Abstract (in Japanese) (See Japanese page) 
(in English) We have been studied the via-programmable-device VPEX (Via Programmable logic using EXclusive or array) whose logic element consists of the combination of complex-gate-type EXOR gate and Inverter. 13 kinds of logic functions including all two-input and one-output functions can be programmed by changing via-1. Register (DFF: D Flip Flops) can be realized by using some LEs. In addition, Various kinds of combination logics are configured by changing via-3 which controls the connection between LEs. However, wiring delay will increase due to this wiring architecture in comparison with the standard ASIC. In this paper, the test circuit to evaluate wiring delay is studied. Furthermore, the delay of the normal-wiring for short path and the bridge-wiring for long path in the VPEX are compared.
Keyword (in Japanese) (See Japanese page) 
(in English) Via-programmable-logic / EB direct writing / Exclusive-OR / Wiring delay / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 462, VLD2009-109, pp. 61-66, March 2010.
Paper # VLD2009-109 
Date of Issue 2010-03-03 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-109

Conference Information
Committee VLD  
Conference Date 2010-03-10 - 2010-03-12 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2010-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Wiring delay of Logic Element used in Via programmable logic device VPEX 
Sub Title (in English)  
Keyword(1) Via-programmable-logic  
Keyword(2) EB direct writing  
Keyword(3) Exclusive-OR  
Keyword(4) Wiring delay  
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1st Author's Name Tomohiro Nishimoto  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan Univ)
2nd Author's Name Tatsuya Kitamori  
2nd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ)
3rd Author's Name Yuuichi Kokushou  
3rd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ)
4th Author's Name Shouta Yamada  
4th Author's Affiliation Ritsumeikan University (Ritsumeikan Univ)
5th Author's Name Masaya Yoshikawa  
5th Author's Affiliation Meijou University (Meijou Univ)
6th Author's Name Takeshi Fujino  
6th Author's Affiliation Ritsumeikan University (Ritsumeikan Univ)
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Speaker Author-1 
Date Time 2010-03-11 10:50:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2009-109 
Volume (vol) vol.109 
Number (no) no.462 
Page pp.61-66 
#Pages 6 
Date of Issue 2010-03-03 (VLD) 

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