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Paper Abstract and Keywords
Presentation 2010-03-11 11:15
High-Level Synthesis of Programmable Hardware Accelerators Considering Potential Varieties
Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST) VLD2009-110
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, programmable hardware accelerators have attracted more attention as an enabling solution for post-silicon engineering change, manufacturing defect tolerance, and efficient hardware reuse. Since existing techniques synthesize for a specific application, the synthesized hardware may not satisfy the performance goal under potential varieties such as engineering changes and manufacturing defects. This paper proposes a synthesis methodology of programmable hardware accelerators which maximizes the performance yield under potential varieties. Experimental results demonstrate that our methodology can improve the performance yield significantly with a small area increase.
Keyword (in Japanese) (See Japanese page) 
(in English) Programmable hardware accelerators / engineering changes / high-level synthesis / performance yield / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 462, VLD2009-110, pp. 67-72, March 2010.
Paper # VLD2009-110 
Date of Issue 2010-03-03 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-110

Conference Information
Committee VLD  
Conference Date 2010-03-10 - 2010-03-12 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2010-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) High-Level Synthesis of Programmable Hardware Accelerators Considering Potential Varieties 
Sub Title (in English)  
Keyword(1) Programmable hardware accelerators  
Keyword(2) engineering changes  
Keyword(3) high-level synthesis  
Keyword(4) performance yield  
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1st Author's Name Hiroaki Yoshida  
1st Author's Affiliation University of Tokyo/CREST, Japan Science and Technology Agency (Univ. of Tokyo/JST)
2nd Author's Name Masahiro Fujita  
2nd Author's Affiliation University of Tokyo/CREST, Japan Science and Technology Agency (Univ. of Tokyo/JST)
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Speaker Author-1 
Date Time 2010-03-11 11:15:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2009-110 
Volume (vol) vol.109 
Number (no) no.462 
Page pp.67-72 
#Pages 6 
Date of Issue 2010-03-03 (VLD) 

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