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Paper Abstract and Keywords
Presentation 2010-03-12 15:00
An ASIC implementation of a group signature algorithm using two-level behavioral synthesis
Sumio Morioka, Toshinori Araki, Toshiyuki Isshiki, Satoshi Obana, Kazue Sako (NEC) VLD2009-128
Abstract (in Japanese) (See Japanese page) 
(in English) We implemented a group signature algorithm, which enables anonymous digital signature, into an ASIC. To the best of the authors' knowledge, there has been no report on H/W design of the group signature. The signature algorithm is too complicated to use a standard RTL entry nor a behavioral synthesis method in the front-end design. We incorporated
a two-level behavioral synthesis approach, where the circuit's macro-architecture is generated by a custom-made scheduler and the micro-architecture is constructed by a standard behavioral synthesis. Our 0.25um gate-array ASIC can generate a digital signature at the equivalent speed (0.135 seconds) with 3GHz PC software, while the power consumption
is two orders of magnitude lower (425mW@100MHz).
Keyword (in Japanese) (See Japanese page) 
(in English) Security / Group signature / ESL / HLS / Architecture synthesis / Behavioral synthesis / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 462, VLD2009-128, pp. 175-180, March 2010.
Paper # VLD2009-128 
Date of Issue 2010-03-03 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-128

Conference Information
Committee VLD  
Conference Date 2010-03-10 - 2010-03-12 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2010-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An ASIC implementation of a group signature algorithm using two-level behavioral synthesis 
Sub Title (in English)  
Keyword(1) Security  
Keyword(2) Group signature  
Keyword(3) ESL  
Keyword(4) HLS  
Keyword(5) Architecture synthesis  
Keyword(6) Behavioral synthesis  
Keyword(7)  
Keyword(8)  
1st Author's Name Sumio Morioka  
1st Author's Affiliation System IP Core Research Labs., NEC (NEC)
2nd Author's Name Toshinori Araki  
2nd Author's Affiliation Common Platform Software Research Labs., NEC (NEC)
3rd Author's Name Toshiyuki Isshiki  
3rd Author's Affiliation Common Platform Software Research Labs., NEC (NEC)
4th Author's Name Satoshi Obana  
4th Author's Affiliation Common Platform Software Research Labs., NEC (NEC)
5th Author's Name Kazue Sako  
5th Author's Affiliation Common Platform Software Research Labs., NEC (NEC)
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Speaker Author-1 
Date Time 2010-03-12 15:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2009-128 
Volume (vol) vol.109 
Number (no) no.462 
Page pp.175-180 
#Pages 6 
Date of Issue 2010-03-03 (VLD) 

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