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Paper Abstract and Keywords
Presentation 2010-03-28 13:00
Design of Look-Ahead Router for Low Latency Real-Time On-Chip Networks
Takuma Kogo, Nobuyuki Yamasaki (Keio Univ.) CPSY2009-89 DC2009-86
Abstract (in Japanese) (See Japanese page) 
(in English) Scheduling algorithms are very important to realize a real-time system by using large-scale chip multiprocessors (CMPs). Most real-time scheduling algorithms assume preemption and worst-case execution time. It is challenging topic to handle these requirements on Networks-on-Chip (NoC) which interconnects each core in large-scale CMP, because some
on-chip constraints exist including amount of hardware and energy. Preemption mechanism may decrease throughput and increase latency. As result, application performance may fall down. This paper proposes a look-ahead on-chip router for a preemptable NoC. Proposed scheme reduces a number of pipeline stages and improves latency. We implemented the look-ahead on-chip router by using HDL and evaluated it by using synthetic traffics.
Keyword (in Japanese) (See Japanese page) 
(in English) Real-Time / Multi-core / Many-core / On-chip Networks / Networks-on-Chip (NoC) / Low Latency / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 474, CPSY2009-89, pp. 465-470, March 2010.
Paper # CPSY2009-89 
Date of Issue 2010-03-19 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2009-89 DC2009-86

Conference Information
Committee CPSY DC IPSJ-SLDM IPSJ-EMB IPSJ-UBI IPSJ-MBL  
Conference Date 2010-03-26 - 2010-03-28 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To CPSY 
Conference Code 2010-03-CPSY-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of Look-Ahead Router for Low Latency Real-Time On-Chip Networks 
Sub Title (in English)  
Keyword(1) Real-Time  
Keyword(2) Multi-core  
Keyword(3) Many-core  
Keyword(4) On-chip Networks  
Keyword(5) Networks-on-Chip (NoC)  
Keyword(6) Low Latency  
Keyword(7)  
Keyword(8)  
1st Author's Name Takuma Kogo  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Nobuyuki Yamasaki  
2nd Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2010-03-28 13:00:00 
Presentation Time 20 minutes 
Registration for CPSY 
Paper # CPSY2009-89, DC2009-86 
Volume (vol) vol.109 
Number (no) no.474(CPSY), no.475(DC) 
Page pp.465-470 
#Pages 6 
Date of Issue 2010-03-19 (CPSY, DC) 

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