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Paper Abstract and Keywords
Presentation 2010-04-13 13:30
[Invited Talk] Increasing Dependability based on Asynchronous Computation
Tomohiro Yoneda (NII/Tokyo Tech.) CPSY2010-1 DC2010-1
Abstract (in Japanese) (See Japanese page) 
(in English) As semiconductor process technology scales and device dimensions shrink, new types of faults, such as slow transistors due to process parameter variation, performance degradation caused by PMOS transistor negative bias temperature instability (NBTI), soft errors, and so on, become a key reliability concern. This talk addresses how asynchronous circuit technology can be used to tolerate those faults. First of all, the idea of the asynchronous computation is introduced, and then, it is described how circuits based on dual-rail encoding method are implemented and work. Since those circuits can perfectly detect the completion of the computation, any degradation faults can be tolerated. With some additional circuitry, they can also manage some soft-errors and stuck-at-faults. Next, three examples are introduced to show how those technologies can be applied to concrete systems. In the first example, a functional unit is redesigned using dual-rail encoding method, and it is embedded in a synchronous processor with a pausable clock system. Since the pausable clock system appropriately stops the clock until the computation completes, the degradation tolerance can be achieved easily in synchronous systems. Second, a fully asynchronous approach is used to implement a linear equation solver with high degradation tolerance. In this design, several identical functional units are used to perform the computation concurrently. When one functional unit is degraded, data-flow is autonomously controlled such that less data is sent to the degraded unit, and the whole computation can be performed without large additional delay. Finally, several issues related to the application of asynchronous circuit technologies in the NoC (Networks-on-Chip) area are discussed.
Keyword (in Japanese) (See Japanese page) 
(in English) Dual-rail code / Delay variation / Degradation / Pausable clock / Networks on Chip / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 3, DC2010-1, pp. 1-1, April 2010.
Paper # DC2010-1 
Date of Issue 2010-04-06 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC CPSY  
Conference Date 2010-04-13 - 2010-04-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2010-04-DC-CPSY 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Increasing Dependability based on Asynchronous Computation 
Sub Title (in English)  
Keyword(1) Dual-rail code  
Keyword(2) Delay variation  
Keyword(3) Degradation  
Keyword(4) Pausable clock  
Keyword(5) Networks on Chip  
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1st Author's Name Tomohiro Yoneda  
1st Author's Affiliation National Institute of Infomatics/Tokyo Institute of Technology (NII/Tokyo Tech.)
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Speaker Author-1 
Date Time 2010-04-13 13:30:00 
Presentation Time 60 minutes 
Registration for DC 
Paper # CPSY2010-1, DC2010-1 
Volume (vol) vol.110 
Number (no) no.2(CPSY), no.3(DC) 
Page p.1 
#Pages
Date of Issue 2010-04-06 (CPSY, DC) 


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