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| Presentation | 2010-04-22 09:50 [Invited Talk] Challenging for an ultra low-voltage SRAM by innovative design circuits and device technologies -- A 0.5V 100MHz PD-SOI SRAM using Asymmetric MOSFET and Forward Body Bias -- Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Yuuichi Hirano, Toshiaki Iwamatsu, Yuji Kihara (Renesas Electronics)  ICD2010-2 Link to ES Tech. Rep. Archives: ICD2010-2 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We investigate 0.5V 6T-SRAM with asymmetric MOSFET, which contributes to enhance the read and write margin. We also introduce a forward body bias technique not only bitcell arrays but also peripheral circuits. Test chips are designed and fabricated using 90-nm PD-SOI technology. The measurement results show minimum operating voltage of proposed SRAM was 0.45V at 25 C, which is 100mV lower than conventional SRAM, and the access time was 6.8ns at 0.5V. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | SRAM / Low-power / SOI / VCCmin / Asymmetric / Forward Body Bias / Halo / 0.5V | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 9, ICD2010-2, pp. 7-12, April 2010. | |
| Paper # | ICD2010-2 | |
| Date of Issue | 2010-04-15 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ICD2010-2 Link to ES Tech. Rep. Archives: ICD2010-2 |
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| Conference Information | |
| Committee | ICD |
| Conference Date | 2010-04-22 - 2010-04-23 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Shonan Institute of Tech. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Memory Device Technologies |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2010-04-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Challenging for an ultra low-voltage SRAM by innovative design circuits and device technologies |
| Sub Title (in English) | A 0.5V 100MHz PD-SOI SRAM using Asymmetric MOSFET and Forward Body Bias |
| Keyword(1) | SRAM |
| Keyword(2) | Low-power |
| Keyword(3) | SOI |
| Keyword(4) | VCCmin |
| Keyword(5) | Asymmetric |
| Keyword(6) | Forward Body Bias |
| Keyword(7) | Halo |
| Keyword(8) | 0.5V |
| 1st Author's Name | Koji Nii |
| 1st Author's Affiliation | Renesas Electronics (Renesas Electronics) |
| 2nd Author's Name | Makoto Yabuuchi |
| 2nd Author's Affiliation | Renesas Electronics (Renesas Electronics) |
| 3rd Author's Name | Yasumasa Tsukamoto |
| 3rd Author's Affiliation | Renesas Electronics (Renesas Electronics) |
| 4th Author's Name | Yuuichi Hirano |
| 4th Author's Affiliation | Renesas Electronics (Renesas Electronics) |
| 5th Author's Name | Toshiaki Iwamatsu |
| 5th Author's Affiliation | Renesas Electronics (Renesas Electronics) |
| 6th Author's Name | Yuji Kihara |
| 6th Author's Affiliation | Renesas Electronics (Renesas Electronics) |
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| Speaker | Author-1 |
| Date Time | 2010-04-22 09:50:00 |
| Presentation Time | 50 minutes |
| Registration for | ICD |
| Paper # | ICD2010-2 |
| Volume (vol) | vol.110 |
| Number (no) | no.9 |
| Page | pp.7-12 |
| #Pages | 6 |
| Date of Issue | 2010-04-15 (ICD) |
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