Paper Abstract and Keywords |
Presentation |
2010-05-14 11:20
GALS Design for Scalable Array Processors Operating on Multiple FPGAs Wang Luzhou, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) RECONF2010-13 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
So far we have proposed systolic computational-memory (SCM) architecture for high-performance and scalable computation based on the finite difference methods. The SCM architecture has a completely parallel array structure to achieve scalable performance to the increased hardware resources of a multi-FPGA system. The problem is that real-world implementation requires globally asynchronous and locally synchronous (GALS) design for scalably operating over multiple FPGAs with different clock domains. This paper presents GALS design of SCM arrays (SCMA) for asynchronous communication and a stall mechanism to guarantee the data synchronization among processing elements of different clock domains. Prototype implementation with ALTERA Stratix III FPGAs shows that the proposed design does not give a big overhead in operating frequency and hardware resource utilization. We also evaluate the scalability of the SCMA over multiple FPGAs considering actual stall cycles. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
custom computing machines / difference scheme / FPGA / GALS / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 32, RECONF2010-13, pp. 69-74, May 2010. |
Paper # |
RECONF2010-13 |
Date of Issue |
2010-05-06 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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RECONF2010-13 |
Conference Information |
Committee |
RECONF |
Conference Date |
2010-05-13 - 2010-05-14 |
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(See Japanese page) |
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RECONF |
Conference Code |
2010-05-RECONF |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
GALS Design for Scalable Array Processors Operating on Multiple FPGAs |
Sub Title (in English) |
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custom computing machines |
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difference scheme |
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FPGA |
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GALS |
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1st Author's Name |
Wang Luzhou |
1st Author's Affiliation |
Tohoku University (Tohoku Univ.) |
2nd Author's Name |
Kentaro Sano |
2nd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
3rd Author's Name |
Satoru Yamamoto |
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Tohoku University (Tohoku Univ.) |
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Speaker |
Author-1 |
Date Time |
2010-05-14 11:20:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2010-13 |
Volume (vol) |
vol.110 |
Number (no) |
no.32 |
Page |
pp.69-74 |
#Pages |
6 |
Date of Issue |
2010-05-06 (RECONF) |