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Paper Abstract and Keywords
Presentation 2010-05-14 14:20
Fabrication of 1-bit counter circuit with LED indicator using Si/III-V-N/Si structure
Seizo Tanaka, Kenta Noguchi, Keisuke Yamane, Yuki Deguchi, Yuzo Furukawa, Hiroshi Okada, Akihiro Wakahara, Hiroo Yonezu (Toyohashi Univ. of Tech.) ED2010-32 CPM2010-22 SDM2010-32 Link to ES Tech. Rep. Archives: ED2010-32 CPM2010-22 SDM2010-32
Abstract (in Japanese) (See Japanese page) 
(in English) We fabricated of 1-bit counter circuit with light-emitting diode (LED) indicators using semiconductor process technology for a Si/III-V-N/Si structure. This circuit was designed with p-type metal oxide semiconductor field effect transistors and LEDs. As a result , the 1-bit counter circuit was normally operated at a driving voltage of 6.2 V. The light emission from LED indicators were synchronized with the input and output signals of the 1-bit counter circuit. These results imply that the Si-based digital circuit and III-V-N-based LEDs can be monolithically integrated a single chip.
Keyword (in Japanese) (See Japanese page) 
(in English) Si / OEIC / GaPN / Si/III-V-N/Si structure / monolithic / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 31, SDM2010-32, pp. 81-85, May 2010.
Paper # SDM2010-32 
Date of Issue 2010-05-06 (ED, CPM, SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ED2010-32 CPM2010-22 SDM2010-32 Link to ES Tech. Rep. Archives: ED2010-32 CPM2010-22 SDM2010-32

Conference Information
Committee SDM CPM ED  
Conference Date 2010-05-13 - 2010-05-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Shizuoka University (Hamamatsu Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Crystal growth, evaluation and device (Compound, Si, SiGe, Electronic and light emitting materials) 
Paper Information
Registration To SDM 
Conference Code 2010-05-SDM-CPM-ED 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Fabrication of 1-bit counter circuit with LED indicator using Si/III-V-N/Si structure 
Sub Title (in English)  
Keyword(1) Si  
Keyword(2) OEIC  
Keyword(3) GaPN  
Keyword(4) Si/III-V-N/Si structure  
Keyword(5) monolithic  
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Keyword(7)  
Keyword(8)  
1st Author's Name Seizo Tanaka  
1st Author's Affiliation Toyohashi University of Technology (Toyohashi Univ. of Tech.)
2nd Author's Name Kenta Noguchi  
2nd Author's Affiliation Toyohashi University of Technology (Toyohashi Univ. of Tech.)
3rd Author's Name Keisuke Yamane  
3rd Author's Affiliation Toyohashi University of Technology (Toyohashi Univ. of Tech.)
4th Author's Name Yuki Deguchi  
4th Author's Affiliation Toyohashi University of Technology (Toyohashi Univ. of Tech.)
5th Author's Name Yuzo Furukawa  
5th Author's Affiliation Toyohashi University of Technology (Toyohashi Univ. of Tech.)
6th Author's Name Hiroshi Okada  
6th Author's Affiliation Toyohashi University of Technology (Toyohashi Univ. of Tech.)
7th Author's Name Akihiro Wakahara  
7th Author's Affiliation Toyohashi University of Technology (Toyohashi Univ. of Tech.)
8th Author's Name Hiroo Yonezu  
8th Author's Affiliation Toyohashi University of Technology (Toyohashi Univ. of Tech.)
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Speaker Author-1 
Date Time 2010-05-14 14:20:00 
Presentation Time 25 minutes 
Registration for SDM 
Paper # ED2010-32, CPM2010-22, SDM2010-32 
Volume (vol) vol.110 
Number (no) no.29(ED), no.30(CPM), no.31(SDM) 
Page pp.81-85 
#Pages
Date of Issue 2010-05-06 (ED, CPM, SDM) 


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