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Paper Abstract and Keywords
Presentation 2010-06-25 14:00
A Class of Partial Thru Testable Sequential Circuits with Multiplexers
Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2010-9
Abstract (in Japanese) (See Japanese page) 
(in English) Partially thru testable sequential circuits are known to be practically testable, and a condition for the testable sequential circuits has been proposed. In this paper, we focus on multiplexers in partially thru testable sequential circuits, and show that a part of the condition, which is a sub-condition about the hold function of registers, can be relaxed by considering the function of multiplexers.
A class of the sequential circuits that satisfy the relaxed condition includes the previous class of partially thru testable circuits.
Experimental results show that a DFT based on the new class requires smaller area overhead and smaller test application time than that based on the previous class.
Keyword (in Japanese) (See Japanese page) 
(in English) thru testability / design for testability / time expansion model / combinational test generation algorithm / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 106, DC2010-9, pp. 7-11, June 2010.
Paper # DC2010-9 
Date of Issue 2010-06-18 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF DC2010-9

Conference Information
Committee DC  
Conference Date 2010-06-25 - 2010-06-25 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2010-06-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Class of Partial Thru Testable Sequential Circuits with Multiplexers 
Sub Title (in English)  
Keyword(1) thru testability  
Keyword(2) design for testability  
Keyword(3) time expansion model  
Keyword(4) combinational test generation algorithm  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Nobuya Oka  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Yuki Yoshikawa  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Hideyuki Ichihara  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
4th Author's Name Tomoo Inoue  
4th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
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Speaker Author-1 
Date Time 2010-06-25 14:00:00 
Presentation Time 30 minutes 
Registration for DC 
Paper # DC2010-9 
Volume (vol) vol.110 
Number (no) no.106 
Page pp.7-11 
#Pages 5 
Date of Issue 2010-06-18 (DC) 

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