講演抄録/キーワード |
講演名 |
2010-07-02 16:05
The optimum physical targets of the 3-dimensional vertical FG NAND flash memory cell arrays with the extended sidewall control gate (ESCG) structure ○Moon-Sik Seo(Tohoku Univ.)・Tetsuo Endoh(Tohoku Univ./JST) ED2010-101 SDM2010-102 エレソ技報アーカイブへのリンク:ED2010-101 SDM2010-102 |
抄録 |
(和) |
Recently, the 3-dimensional vertical Floating Gate (FG) NAND flash memory cell arrays with the extended sidewall control gate (ESCG) was proposed. Using this novel structure, we successfully implemented superior program speed, read current, and less interference characteristics, by the high coupling ratio and highly electrical inverted S/D region. However, the process stability of the ESCG structure has not been sufficiently confirmed such as the variations of the physical dimensions.
In this paper, we intensively investigated the electrical dependency according to the physical dimensions of ESCG, such as the line and spacing of ESCG, the thickness of bottom oxide and so on. Using the 2-dimentional TCAD simulations, we compared the basic characteristics of the FG type flash cell operation, in the aspect of program speed, read current, and interference effect. Finally, we check the process window and suggest the optimum target of the ESCG structure for reliable flash cell operation. From above all, we confirmed that this 3-dimensional vertical FG NAND flash memory cell arrays using the ESCG structure is the most attractive candidate for terabit 3-D vertical NAND flash cell array. |
(英) |
Recently, the 3-dimensional vertical Floating Gate (FG) NAND flash memory cell arrays with the extended sidewall control gate (ESCG) was proposed. Using this novel structure, we successfully implemented superior program speed, read current, and less interference characteristics, by the high coupling ratio and highly electrical inverted S/D region. However, the process stability of the ESCG structure has not been sufficiently confirmed such as the variations of the physical dimensions.
In this paper, we intensively investigated the electrical dependency according to the physical dimensions of ESCG, such as the line and spacing of ESCG, the thickness of bottom oxide and so on. Using the 2-dimentional TCAD simulations, we compared the basic characteristics of the FG type flash cell operation, in the aspect of program speed, read current, and interference effect. Finally, we check the process window and suggest the optimum target of the ESCG structure for reliable flash cell operation. From above all, we confirmed that this 3-dimensional vertical FG NAND flash memory cell arrays using the ESCG structure is the most attractive candidate for terabit 3-D vertical NAND flash cell array. |
キーワード |
(和) |
Stacked-Surrounding Gate cell / 3-dimensional vertical Floating Gate (FG) type NAND flash / Extended Sidewall Control Gate (ESCG) / / / / / |
(英) |
Stacked-Surrounding Gate cell / 3-dimensional vertical Floating Gate (FG) type NAND flash / Extended Sidewall Control Gate (ESCG) / / / / / |
文献情報 |
信学技報, vol. 110, no. 110, SDM2010-102, pp. 225-230, 2010年6月. |
資料番号 |
SDM2010-102 |
発行日 |
2010-06-23 (ED, SDM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
ED2010-101 SDM2010-102 エレソ技報アーカイブへのリンク:ED2010-101 SDM2010-102 |
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