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Paper Abstract and Keywords
Presentation 2010-07-02 16:05
The optimum physical targets of the 3-dimensional vertical FG NAND flash memory cell arrays with the extended sidewall control gate (ESCG) structure
Moon-Sik Seo (Tohoku Univ.), Tetsuo Endoh (Tohoku Univ./JST) ED2010-101 SDM2010-102
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, the 3-dimensional vertical Floating Gate (FG) NAND flash memory cell arrays with the extended sidewall control gate (ESCG) was proposed. Using this novel structure, we successfully implemented superior program speed, read current, and less interference characteristics, by the high coupling ratio and highly electrical inverted S/D region. However, the process stability of the ESCG structure has not been sufficiently confirmed such as the variations of the physical dimensions.
In this paper, we intensively investigated the electrical dependency according to the physical dimensions of ESCG, such as the line and spacing of ESCG, the thickness of bottom oxide and so on. Using the 2-dimentional TCAD simulations, we compared the basic characteristics of the FG type flash cell operation, in the aspect of program speed, read current, and interference effect. Finally, we check the process window and suggest the optimum target of the ESCG structure for reliable flash cell operation. From above all, we confirmed that this 3-dimensional vertical FG NAND flash memory cell arrays using the ESCG structure is the most attractive candidate for terabit 3-D vertical NAND flash cell array.
Keyword (in Japanese) (See Japanese page) 
(in English) Stacked-Surrounding Gate cell / 3-dimensional vertical Floating Gate (FG) type NAND flash / Extended Sidewall Control Gate (ESCG) / / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 110, SDM2010-102, pp. 225-230, June 2010.
Paper # SDM2010-102 
Date of Issue 2010-06-23 (ED, SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ED2010-101 SDM2010-102

Conference Information
Committee ED SDM  
Conference Date 2010-06-30 - 2010-07-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Tokyo Inst. of Tech. Ookayama Campus 
Topics (in Japanese) (See Japanese page) 
Topics (in English) 2010 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices 
Paper Information
Registration To SDM 
Conference Code 2010-06-ED-SDM 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) The optimum physical targets of the 3-dimensional vertical FG NAND flash memory cell arrays with the extended sidewall control gate (ESCG) structure 
Sub Title (in English)  
Keyword(1) Stacked-Surrounding Gate cell  
Keyword(2) 3-dimensional vertical Floating Gate (FG) type NAND flash  
Keyword(3) Extended Sidewall Control Gate (ESCG)  
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1st Author's Name Moon-Sik Seo  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Tetsuo Endoh  
2nd Author's Affiliation Tohoku University/JST-CREST (Tohoku Univ./JST)
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Speaker Author-1 
Date Time 2010-07-02 16:05:00 
Presentation Time 15 minutes 
Registration for SDM 
Paper # ED2010-101, SDM2010-102 
Volume (vol) vol.110 
Number (no) no.109(ED), no.110(SDM) 
Page pp.225-230 
#Pages 6 
Date of Issue 2010-06-23 (ED, SDM) 

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