Paper Abstract and Keywords |
Presentation |
2010-07-22 15:50
[Invited Talk]
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer with a Time-Windowed Time-to-Digital Converter Tadashi Maeda, Takashi Tokairin (Renesas Electronics Corporation), Masaki Kitsunezuka (NEC Corp.), Mitsuji Okada (Renesas Electronics Corporation), Muneo Fukaishi (NEC Corp.) ICD2010-29 Link to ES Tech. Rep. Archives: ICD2010-29 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented. The time-windowed TDC uses a 2-step structure with an inverter- and a vernier-delay time-quantizer to improve time resolution, which results in low phase noise. Time-windowed operation is implemented in the TDC, in which a single-shot pulse-based operation is used for low power consumption. The test chip implemented in 90-nm CMOS technology exhibits in-band phase noise of -105 dBc/Hz, where the loop-bandwidth is set to 500 kHz with a 40-MHz reference signal, and out-band noise of -115 dBc/Hz at a 1-MHz offset frequency. The chip core occupies 0.37 mm2 and the measured power consumption is 8.1 mA from a 1.2-V power supply. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
All-digital phase locked loop / digitally controlled oscillator / frequency synthesizer / phase noise / quantization noise / time-to-digital converter / sigma-delta modulator / synchronous counter |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 140, ICD2010-29, pp. 49-54, July 2010. |
Paper # |
ICD2010-29 |
Date of Issue |
2010-07-15 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2010-29 Link to ES Tech. Rep. Archives: ICD2010-29 |
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