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Paper Abstract and Keywords
Presentation 2010-07-22 15:50
[Invited Talk] A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer with a Time-Windowed Time-to-Digital Converter
Tadashi Maeda, Takashi Tokairin (Renesas Electronics Corporation), Masaki Kitsunezuka (NEC Corp.), Mitsuji Okada (Renesas Electronics Corporation), Muneo Fukaishi (NEC Corp.) ICD2010-29
Abstract (in Japanese) (See Japanese page) 
(in English) A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented. The time-windowed TDC uses a 2-step structure with an inverter- and a vernier-delay time-quantizer to improve time resolution, which results in low phase noise. Time-windowed operation is implemented in the TDC, in which a single-shot pulse-based operation is used for low power consumption. The test chip implemented in 90-nm CMOS technology exhibits in-band phase noise of -105 dBc/Hz, where the loop-bandwidth is set to 500 kHz with a 40-MHz reference signal, and out-band noise of -115 dBc/Hz at a 1-MHz offset frequency. The chip core occupies 0.37 mm2 and the measured power consumption is 8.1 mA from a 1.2-V power supply.
Keyword (in Japanese) (See Japanese page) 
(in English) All-digital phase locked loop / digitally controlled oscillator / frequency synthesizer / phase noise / quantization noise / time-to-digital converter / sigma-delta modulator / synchronous counter  
Reference Info. IEICE Tech. Rep., vol. 110, no. 140, ICD2010-29, pp. 49-54, July 2010.
Paper # ICD2010-29 
Date of Issue 2010-07-15 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2010-29

Conference Information
Committee ICD ITE-IST  
Conference Date 2010-07-22 - 2010-07-23 
Place (in Japanese) (See Japanese page) 
Place (in English) Josho Gakuen Osaka Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Analog, Mixed analog and digital, RF, and sensor interface circuitry 
Paper Information
Registration To ICD 
Conference Code 2010-07-ICD-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer with a Time-Windowed Time-to-Digital Converter 
Sub Title (in English)  
Keyword(1) All-digital phase locked loop  
Keyword(2) digitally controlled oscillator  
Keyword(3) frequency synthesizer  
Keyword(4) phase noise  
Keyword(5) quantization noise  
Keyword(6) time-to-digital converter  
Keyword(7) sigma-delta modulator  
Keyword(8) synchronous counter  
1st Author's Name Tadashi Maeda  
1st Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corporation)
2nd Author's Name Takashi Tokairin  
2nd Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corporation)
3rd Author's Name Masaki Kitsunezuka  
3rd Author's Affiliation System IP-core Laboratory, NEC Corporation. (NEC Corp.)
4th Author's Name Mitsuji Okada  
4th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corporation)
5th Author's Name Muneo Fukaishi  
5th Author's Affiliation System IP-core Laboratory, NEC Corporation. (NEC Corp.)
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Speaker Author-1 
Date Time 2010-07-22 15:50:00 
Presentation Time 50 minutes 
Registration for ICD 
Paper # ICD2010-29 
Volume (vol) vol.110 
Number (no) no.140 
Page pp.49-54 
#Pages 6 
Date of Issue 2010-07-15 (ICD) 

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