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| Presentation | 2010-08-26 13:00 1-Tbyte/s 1-Gbit 3-D DRAM Architecture for High Throughput Computing Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Tomonori Sekiguchi (Hitachi)  SDM2010-131 ICD2010-46 Link to ES Tech. Rep. Archives: SDM2010-131 ICD2010-46 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A novel DRAM architecture with an ultra high bandwidth is proposed for high throughput computing. The proposed architecture employs three techniques; 1) 5-stage pipelined 16-DRAM cores, 2) an early bar write scheme for an 8-ns cycle array operation, 3) 16-Gbit/s I/O circuit on each 32 through-silicon-via pairs/DRAM core. We confirmed by the circuit simulation assuming 45-nm 1-Gbit chip that the proposed architecture achieves 1-Tbyte/s bandwidth with 19.5-W power consumption. The chip area is estimated to be 52mm2. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | DRAM / 3-D interconnect / through silicon via / throughput computing / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 183, ICD2010-46, pp. 39-44, Aug. 2010. | |
| Paper # | ICD2010-46 | |
| Date of Issue | 2010-08-19 (SDM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2010-131 ICD2010-46 Link to ES Tech. Rep. Archives: SDM2010-131 ICD2010-46 |
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| Conference Information | |
| Committee | ICD SDM |
| Conference Date | 2010-08-26 - 2010-08-27 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Sapporo Center for Gender Equality |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Low voltage/low power techniques, novel devices, circuits, and applications |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2010-08-ICD-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 1-Tbyte/s 1-Gbit 3-D DRAM Architecture for High Throughput Computing |
| Sub Title (in English) | |
| Keyword(1) | DRAM |
| Keyword(2) | 3-D interconnect |
| Keyword(3) | through silicon via |
| Keyword(4) | throughput computing |
| Keyword(5) | |
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| 1st Author's Name | Yoshimitsu Yanagawa |
| 1st Author's Affiliation | Hitachi, Ltd. (Hitachi) |
| 2nd Author's Name | Kazuo Ono |
| 2nd Author's Affiliation | Hitachi, Ltd. (Hitachi) |
| 3rd Author's Name | Akira Kotabe |
| 3rd Author's Affiliation | Hitachi, Ltd. (Hitachi) |
| 4th Author's Name | Tomonori Sekiguchi |
| 4th Author's Affiliation | Hitachi, Ltd. (Hitachi) |
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| Speaker | Author-1 |
| Date Time | 2010-08-26 13:00:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | SDM2010-131, ICD2010-46 |
| Volume (vol) | vol.110 |
| Number (no) | no.182(SDM), no.183(ICD) |
| Page | pp.39-44 |
| #Pages | 6 |
| Date of Issue | 2010-08-19 (SDM, ICD) |
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