Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2010-08-26 09:10
On-Chip Supply Resonance Noise Reduction Method for Multi-IP Cores utilizing Parasitic Capacitance of Sleep Blocks
Jinmyoung Kim, Toru Nakura (Univ. of Tokyo.), Hidehiro Takata, Koichiro Ishibashi (Renesas Electronics), Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo.) SDM2010-124 ICD2010-39
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes an on-chip supply resonance noise reduction method for multi-IP cores utilizing parasitic capacitance of sleep blocks. It has smaller area penalty than conventional on-chip large MOS capacitors because we use parasitic capacitance of sleep blocks for noise cancelling. Measurement results show that the test chip fabricated in a 0.18um CMOS process achieved 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. These results make fast power mode transition possible for dynamic voltage scaling and power gating.
Keyword (in Japanese) (See Japanese page) 
(in English) Power supply noise / resonance / parasitic capacitance / sleep block / DVS / power gating / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 183, ICD2010-39, pp. 1-4, Aug. 2010.
Paper # ICD2010-39 
Date of Issue 2010-08-19 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2010-124 ICD2010-39

Conference Information
Committee ICD SDM  
Conference Date 2010-08-26 - 2010-08-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Sapporo Center for Gender Equality 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Low voltage/low power techniques, novel devices, circuits, and applications 
Paper Information
Registration To ICD 
Conference Code 2010-08-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) On-Chip Supply Resonance Noise Reduction Method for Multi-IP Cores utilizing Parasitic Capacitance of Sleep Blocks 
Sub Title (in English)  
Keyword(1) Power supply noise  
Keyword(2) resonance  
Keyword(3) parasitic capacitance  
Keyword(4) sleep block  
Keyword(5) DVS  
Keyword(6) power gating  
Keyword(7)  
Keyword(8)  
1st Author's Name Jinmyoung Kim  
1st Author's Affiliation The University of Tokyo (Univ. of Tokyo.)
2nd Author's Name Toru Nakura  
2nd Author's Affiliation VLSI Design and Education Center, the University of Tokyo (Univ. of Tokyo.)
3rd Author's Name Hidehiro Takata  
3rd Author's Affiliation Design Platform Development Division, Renesas Electronics Corporation (Renesas Electronics)
4th Author's Name Koichiro Ishibashi  
4th Author's Affiliation Design Platform Development Division, Renesas Electronics Corporation (Renesas Electronics)
5th Author's Name Makoto Ikeda  
5th Author's Affiliation The University of Tokyo (Univ. of Tokyo.)
6th Author's Name Kunihiro Asada  
6th Author's Affiliation The University of Tokyo (Univ. of Tokyo.)
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2010-08-26 09:10:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # SDM2010-124, ICD2010-39 
Volume (vol) vol.110 
Number (no) no.182(SDM), no.183(ICD) 
Page pp.1-4 
#Pages 4 
Date of Issue 2010-08-19 (SDM, ICD) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan