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Paper Abstract and Keywords
Presentation 2010-09-17 10:15
Structure of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture
Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2010-33
Abstract (in Japanese) (See Japanese page) 
(in English) Asynchronous circuit is power-efficient for low-workload sub-circuits since there is no power consumption of the clock tree. On the other hand, synchronous circuit is power-efficient for high-workload sub-circuits since its simple hardware. Exploiting the advantages of the synchronous circuit and the asynchronous circuit, each sub-circuit of the proposed FPGA performs as either synchronous circuit or asynchronous circuit according to its workload. Since the hardware amount of the asynchronous circuit is about double that of the synchronous circuit, the major concern is designing the functional unit which is efficient for both asynchronous and synchronous circuits. In order to fully exploiting the hardware resources, in the proposed FPGA, a functional unit can be selected to perform as either a single asynchronous four-input LUT or two synchronous four-input LUTs.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / reconfigurable VLSI / asynchronous architecture / four-phase dual-rail encoding / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 204, RECONF2010-33, pp. 91-95, Sept. 2010.
Paper # RECONF2010-33 
Date of Issue 2010-09-09 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2010-33

Conference Information
Committee RECONF  
Conference Date 2010-09-16 - 2010-09-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Shizuoka University (Faculty of Eng., Hall 2) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2010-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Structure of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) reconfigurable VLSI  
Keyword(3) asynchronous architecture  
Keyword(4) four-phase dual-rail encoding  
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1st Author's Name Shota Ishihara  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Ryoto Tsuchiya  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Yoshiya Komatsu  
3rd Author's Affiliation Tohoku University (Tohoku Univ.)
4th Author's Name Masanori Hariyama  
4th Author's Affiliation Tohoku University (Tohoku Univ.)
5th Author's Name Michitaka Kameyama  
5th Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker Author-1 
Date Time 2010-09-17 10:15:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2010-33 
Volume (vol) vol.110 
Number (no) no.204 
Page pp.91-95 
#Pages 5 
Date of Issue 2010-09-09 (RECONF) 

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