講演抄録/キーワード |
講演名 |
2010-09-22 16:10
A Low-power and Performance-aware DVB-S2 LDPC Decoder with Layered Scheduling ○Xiongxin Zhao・Zhixiang Chen・Xiao Peng・Dajiang Zhou・Satoshi Goto(Waseda Univ.) IT2010-49 |
抄録 |
(和) |
(まだ登録されていません) |
(英) |
In this paper we propose an LDPC decoder for DVB-S2 with layered decoding schedule. A particular data updating mechanism for DVB-S2 is introduced to avoid all data updating conflicts without any approximation which worsens the BER performance of decoding. The proposed decoder utilizes the most popular partial-parallel layered decoder architecture and can achieve a decoding throughput larger than 105Mbps at 300MHz with acceptable hardware and clock overhead. Moreover, the proposed architecture shows great potential for performance-aware and low-power design. |
キーワード |
(和) |
/ / / / / / / |
(英) |
low-density parity-check / layered message passing algorithm / DVB-S2 / / / / / |
文献情報 |
信学技報, vol. 110, no. 205, IT2010-49, pp. 93-97, 2010年9月. |
資料番号 |
IT2010-49 |
発行日 |
2010-09-14 (IT) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
IT2010-49 |