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Paper Abstract and Keywords
Presentation 2010-09-22 16:10
A Low-power and Performance-aware DVB-S2 LDPC Decoder with Layered Scheduling
Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto (Waseda Univ.) IT2010-49
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper we propose an LDPC decoder for DVB-S2 with layered decoding schedule. A particular data updating mechanism for DVB-S2 is introduced to avoid all data updating conflicts without any approximation which worsens the BER performance of decoding. The proposed decoder utilizes the most popular partial-parallel layered decoder architecture and can achieve a decoding throughput larger than 105Mbps at 300MHz with acceptable hardware and clock overhead. Moreover, the proposed architecture shows great potential for performance-aware and low-power design.
Keyword (in Japanese) (See Japanese page) 
(in English) low-density parity-check / layered message passing algorithm / DVB-S2 / / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 205, IT2010-49, pp. 93-97, Sept. 2010.
Paper # IT2010-49 
Date of Issue 2010-09-14 (IT) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF IT2010-49

Conference Information
Committee IT  
Conference Date 2010-09-21 - 2010-09-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Tohoku Gakuin University 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To IT 
Conference Code 2010-09-IT 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Low-power and Performance-aware DVB-S2 LDPC Decoder with Layered Scheduling 
Sub Title (in English)  
Keyword(1) low-density parity-check  
Keyword(2) layered message passing algorithm  
Keyword(3) DVB-S2  
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1st Author's Name Xiongxin Zhao  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Zhixiang Chen  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Xiao Peng  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Dajiang Zhou  
4th Author's Affiliation Waseda University (Waseda Univ.)
5th Author's Name Satoshi Goto  
5th Author's Affiliation Waseda University (Waseda Univ.)
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Speaker Author-1 
Date Time 2010-09-22 16:10:00 
Presentation Time 25 minutes 
Registration for IT 
Paper # IT2010-49 
Volume (vol) vol.110 
Number (no) no.205 
Page pp.93-97 
#Pages 5 
Date of Issue 2010-09-14 (IT) 

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