Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2010-09-28 15:00
Analysis and Evaluation of Simultaneous Switching Noise of FPGA
Yo Takahashi, Toshio Sudo (SIT), Kunio Ota, Kazuhisa Matsuge (Toshiba) VLD2010-54
Abstract (in Japanese) (See Japanese page) 
(in English) FPGAs(Field Programmable Gate Array) are now widely used to digital products. The FPGAs are constituted by CMOS circuit causes SSN(simultaneous Switching Noise) when the output buffers switched simultaneously. In this paper, accuracy of simulating Simultaneous Switching Noise was improved. We exactly estimated the on-chip capacitance and inductance of lead-frames in the QFP(Quad Flat Package). Moreover, the delay of the high time of output waveform causes by the parasitic inductance of the package ware confirmed.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Simultaneous Switching Noise / QFP / Simulation / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 210, VLD2010-54, pp. 71-76, Sept. 2010.
Paper # VLD2010-54 
Date of Issue 2010-09-20 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2010-54

Conference Information
Committee VLD  
Conference Date 2010-09-27 - 2010-09-28 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyoto Institute of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Physical design, etc 
Paper Information
Registration To VLD 
Conference Code 2010-09-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Analysis and Evaluation of Simultaneous Switching Noise of FPGA 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Simultaneous Switching Noise  
Keyword(3) QFP  
Keyword(4) Simulation  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yo Takahashi  
1st Author's Affiliation Shibaura Institute of Technology (SIT)
2nd Author's Name Toshio Sudo  
2nd Author's Affiliation Shibaura Institute of Technology (SIT)
3rd Author's Name Kunio Ota  
3rd Author's Affiliation Toshiba Corp. (Toshiba)
4th Author's Name Kazuhisa Matsuge  
4th Author's Affiliation Toshiba Corp. (Toshiba)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2010-09-28 15:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2010-54 
Volume (vol) vol.110 
Number (no) no.210 
Page pp.71-76 
#Pages 6 
Date of Issue 2010-09-20 (VLD) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan